The wave of OpenHW for flexible digital electronic circuits

Silicon microelectronics world is facing a new powerful wave related to OpenHW.
Chips complexity increased the gap between industrialization and training and research, especially in advanced technology nodes.
Main barriers are cost of silicon, EDA complexity and the access to IPs.
The OpenHW faces these challenges with several initiatives such as:
(1) free silicon access (Google-sponsored eFabless Open MPW Program on 130nm CMOS PDK from Skywater),
(2) the offer of free open-source tools for back-end digital design (e.g. OpenLane & OpenRoad) and
(3) the royalty-free open ISA for RISC-V with many different deployment resources (e.g. HDL HW code, SW & OS resources, platforms).
That wave can be used to facilitate the access to flexible digital electronic circuits.
We started building a 4mm PDK on the Smartkem PMOS process together with its personalization for the OpenLane EDA tools and a RISC-V instance.
We expect to offer the to boost the move from silicon designers to the flexible digital integrated circuits domain.

1. The wave of OpenHWfor
flexible digital electronic circuits
Ashkan Rezaee, Joaquín Saiz, Marc Codina, David Castells,
andJordi Carrabina*
[email protected]

2. Goal
•Silicon microelectronics world is facing a new powerful wave related to OpenHW.
•Chips complexity increased the gap between industrialization and training and research,
especially in advanced technology nodes.
•Main barriers are cost of silicon, EDA complexity and the access to IPs.
•The OpenHWfaces these challenges with several initiatives such as:
(1) free silicon access (Google-sponsored eFablessOpen MPW Program on 130nm CMOS PDK from Skywater),
(2) the offer of free open-source tools for back-end digital design (e.g. OpenLane& OpenRoad) and
(3) the royalty-free open ISA for RISC-V with many different deployment resources (e.g. HDL HW code, SW & OS
resources, platforms).
•That wave can be used to facilitate the access to flexible digital electronic circuits.
•We started building a 4m PDK on the SmartkemPMOS process together with its
personalization for the OpenLaneEDA tools and a RISC-V instance.
•We expect to offer the to boost the move from silicon designers to the flexible digital integrated circuits domain.

3. eFabless.com Open MPW Program
•Sponsored by Google, on Open-source PDK for the 130nm CMOS
from Skywater[3],
•Shuttle program is open to anyone, provided that their project is fully
open source and meets the other program requirements.
•Costs for fabrication, packaging, evaluation boards and shipping are
covered by Google. Its currently in its 7th edition.

4. Open-source EDA tools for back-end digital
design.
•OpenLane:
•Derived from the OpenRoadproject [6], consisting in integrating different existing
open-source tools on a reliable methodology to build digital circuits from technology
independent HDL (Verilog) descriptions.
•The success of the eFabless.com Open MPW Program
•Partly due to the use of OpenLaneto build the circuits on the Skywateropen source
130nm PDK.
•The Google SkyWater130A open source PDK, is a joint venture between
Google and SkyWaterTechnology foundry.
•Used by OpenLaneas its default PDK and provides a fully open-source Process
Design Kit and associated materials.
•Designs can be created using this PDK to be later manufactured at
SkyWater'sfacilities.

5. OpenLane
•OpenLaneis an automated RTL to
GDSII flow based on several
components (including
OpenROAD, Yosys, Magic, Netgen,
CVC, SPEF-Extractor, CU-GR,
Klayout) and a number of custom
scripts for design exploration and
optimization.
•The flow performs full ASIC
implementation steps from RTL all
the way down to GDSII.

6. Royalty-free open ISA for RISC-V
•Many different deployment resources (e.g., HDL HW code, SW & OS
resources, prototyping & deployment platforms).
•It boosted up the research of architectures and implementations for
different domains: from ultra-low power devices (e.g., Pulpino[8] or
SERV [9] platforms) to high-performance computer (HPC) oriented to
vectorial processing (e.g.,[10]).

7. DIGITAL CIRCUITS:
SILICON VS. FLEXIBLE ORGANIC ELECTRONICSProcessor
Dev
count
Date
Tech
(nm)
Core
(mm
2
)
Tr
dens
IMECPragmatIC 6502 16392 2022 800 24,9 658
PragmatIC Cortex-M 56340 2021 800 59,2 952
UMan. BNN FlexIC 3500 2020 800 5,86 766
UMan. Dedicated ML 3000 2019 800 5,6 559
IMEC RFIDtag 8000 2017 10000 50,55 34
IMEC 8-bit ALU 4528 2016 5000 225,6 16
Processor Tr count Date
Tech
(nm)
Area
(mm
2
)
Tr
density
Intel 4004 2250 1971 10000 12 188
Intel 8008 3500 1972 10000 14 250
Intel 4040 3000 1974 10000 12 250
TMS 1000 8000 1974 8000 11 727
MOS Tech 6502 4528 1975 8000 21 216
Toshiba TLCS-12 11000 1973 6000 32 344
Motorola 6800 4100 1974 6000 16 256
Intel 8080 6000 1974 6000 20 300
Motorola 6809 9000 1978 5000 21 429
RCA 1802 5000 1976 5000 27 185
Zilog Z80 8500 1976 4000 18 472
Motorola 68000 68000 1979 3500 44 1545
Intel 8085 6500 1976 3000 20 325
Intel 8086 29000 1978 3000 33 879
Intel 8088 29000 1979 3000 33 879
WDC 65C02 11500 1981 3000 6 1917
Intel 80186 55000 1982 3000 60 917
WDC 65C816 22000 1983 3000 9 2444
ARM 1 25000 1985 3000 50 500
Motorola 68020 190000 1984 2000 85 2235
ARM 2 27000 1986 2000 30 893
Intel 80386 275000 1985 1500 104 2644
Intel 80286 134000 1982 1500 49 2735
DEC MultiTitan 180000 1988 1500 61 2951
ARM 3 310000 1989 1500 87 3563
R4000 1350000 1991 1000 213 6338
Motorola 68030 273000 1987 800 102 2676
Intel i960CA 600000 1989 800 143 4196
Hitachi SH-1 600000 1992 800 10 60000
Pentium 3100000 1993 800 294 10544

8. OPEN-PDK FOR SMARTKEM4MM PMOS
•Our design flow is based on building a PDK and tailoring it for OpenLane, the
automated flow from RTL to GDSII.
•OpenLaneis built on a variety of OpenROAD, Yosys, Magic, Netgen, CVC, SPEF-
Extractor, CU-GR, Klayout, and other custom scripts for design exploration and
optimization.
•The flow carries out all ASIC back-end implementation processes, starting with
RTL HDL Verilog code and ending with GDSII descriptions for the layout.
•PDK information follow OpenDB[12] and allows LEF/DEF conversion with
RosettaStonefor
•(1) Creating OpenDBdatabases from bookshelf and PDK information;
•(2) Missing information (e.g., cell types) are populated based on target PDK;
•(3) Existing macro blocks are properly scaled based on placement site definitions; etc.

9. PDK DATA
•Layerstack
•The cell library includes a variety of combinational gates
•(from NOR2 to AOI23) and sequential gates (DFF, DFFS, DFFR)
•Some macrocellsbuilt with them
•Cells operate at 3.3V (supply) and 5V (bias) voltages.
•PVT characterization is currently underway in order to complete the entire
PDK and all cell datasheets.Layer
name
Description Mask
depth
Min
width
Min
spacing
BG Back gate metal (Ti) 100nm 4um 4um
SD Metal layer for SD (Au) 50nm 4um 4um
TG Top gate metal (Au) 50nm 4um 4um
PAS1 Via layer (SU8) 1um 4um 4um
Gate Interconnection metal (Au) 50nm 4um 4um

10. Standard Cell samples
•Inverters
•DFF

11. Exampleon 2 layerP&R on OpenLane:
Synth_ramCOMPLEX example
•GDS file for 5 layers routing
•Core size:472.88x471.04um
2
•GDS file for 2 layers routing
•Core size:1003.26x1001.44 um
2
~4.5x
Synth_ram
Numberofverilogfile(s)1
Numberofwires 2405
Numberofwirebits 4506
Numberofpublicwires40
Numberofpublicwirebits2140
Numberofmemories 0
Numberofmemorybits0
Numberofprocesses 0
Numberofcells 4446
ANDNOT 252
AND 8
DFFE_PP 2080
MUX 2016
NAND 2
NOR 1
NOT 2
ORNOT 4
OR 81

12. Conclusion
•Flexible digital electronic circuits should profit from the OpenHW
wave currently growing in the silicon electronics IC domain. EDA tools,
PDK methodology and virtual components (IPs) can be reused to
allow building complex circuits.
•We contributed to that wave by building a PDK for the Smartkem
4mm PMOS and personalizing it for the OpenLaneEDA tool.
•We expect to offer it as soon as we finally characterize all cells and
agree with Smartkemon its open diffusion.
•We are also currently implementing a RISC-V instance using that PDK
and OpenLane.