Timing analysis
KunalKunaldoshi09
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May 28, 2017
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About This Presentation
The paper describes the basic of Timing analysis like setup time, hold time, delays in logic circuits, timing violations and different types of timing paths like flip-flop to flip-flop path, clock gating path, asynchronous signal path, half cycle path, flip-flop to output path, input to flip-flop pa...
Slide Content
Technical Paper
Static Timing Analysis – A new approach
295 Technical Writing
Kunal A. Doshi
ID - 010821915
Static Timing Analysis – A new approach
295 Technical Writing
Kunal A. Doshi
ID - 010821915
Introduction
In any integrated circuit, more than fifty million gates are embedded which are at picometers distance
from each other. The performance is affected because the wires or logic gates interfere with the nearby
logic gates affecting the circuit functionality. Therefore, the power dissipation, area, timing, reliability
become an important concern. Therefore, the chips have to go through verification and debugging
process to ensure the circuit works properly on silicon. Amongst all these analysis or processes, timing
analysis is very important because it ensures the proper circuit functionality. The paper deals with
different timing checks that the circuit has to go through in designing and testing stage.
Combinational and Sequential Circuits
Every design possesses the sequential parts and the combinational parts. The sequential circuit
possesses flip-flops also called memory elements whereas the combinational part includes logic gates
like NAND gate, NOR gate, EXOR gate, OR gate and so on. These logic gates are combined to implement
various circuits like multipliers, adders, comparators and many such logic blocks. The sequential element
can store data whereas gates produce output instantly when inputs are applied. The gates are used for
computation purpose whereas the memory elements store the computed values. These are some
differences between combinational and sequential elements. The following figures exhibit both circuit
elements.
Fig1 – Combinational Circuit
In any integrated circuit, more than fifty million gates are embedded which are at picometers distance
from each other. The performance is affected because the wires or logic gates interfere with the nearby
logic gates affecting the circuit functionality. Therefore, the power dissipation, area, timing, reliability
become an important concern. Therefore, the chips have to go through verification and debugging
process to ensure the circuit works properly on silicon. Amongst all these analysis or processes, timing
analysis is very important because it ensures the proper circuit functionality. The paper deals with
different timing checks that the circuit has to go through in designing and testing stage.
Combinational and Sequential Circuits
Every design possesses the sequential parts and the combinational parts. The sequential circuit
possesses flip-flops also called memory elements whereas the combinational part includes logic gates
like NAND gate, NOR gate, EXOR gate, OR gate and so on. These logic gates are combined to implement
various circuits like multipliers, adders, comparators and many such logic blocks. The sequential element
can store data whereas gates produce output instantly when inputs are applied. The gates are used for
computation purpose whereas the memory elements store the computed values. These are some
differences between combinational and sequential elements. The following figures exhibit both circuit
elements.
Fig1 – Combinational Circuit
Fig2 – Sequential Circuit
The basic logic elements are described till now. The main concern is the time at which the output is
produced. The correct output is produced whenever every signal appears at the correct instant in the
circuit. For example, in Fig2, if the input ‘Bn’ arrives after one clock cycle with respect to inputs ‘An’ and
‘Cn-1’ then ‘sum’ and ‘carry’ generated is incorrect. Therefore, the paper deals with such issues which
are responsible for producing incorrect output. The next section describes about the basic terms used in
this analysis.
Basic Terms
In order to understand the timing, it is mandatory to understand few basic terms related to it. The basic
terms are subdivided into different categories. First and foremost, it is important to understand the
different timing analysis types described in the following section.
Timing Analysis Types
1. Dynamic Timing Analysis (DTA)
The dynamic timing analysis is used to check whether the output obtained is correct after inputs
are applied. This analysis concentrates on checking the circuit functionality. For example,
consider a full adder circuit, the DTA checks whether the adder produces correct output for
different stimulus applied. But it fails to check the gate delay involved to produce the output.
The basic logic elements are described till now. The main concern is the time at which the output is
produced. The correct output is produced whenever every signal appears at the correct instant in the
circuit. For example, in Fig2, if the input ‘Bn’ arrives after one clock cycle with respect to inputs ‘An’ and
‘Cn-1’ then ‘sum’ and ‘carry’ generated is incorrect. Therefore, the paper deals with such issues which
are responsible for producing incorrect output. The next section describes about the basic terms used in
this analysis.
Basic Terms
In order to understand the timing, it is mandatory to understand few basic terms related to it. The basic
terms are subdivided into different categories. First and foremost, it is important to understand the
different timing analysis types described in the following section.
Timing Analysis Types
1. Dynamic Timing Analysis (DTA)
The dynamic timing analysis is used to check whether the output obtained is correct after inputs
are applied. This analysis concentrates on checking the circuit functionality. For example,
consider a full adder circuit, the DTA checks whether the adder produces correct output for
different stimulus applied. But it fails to check the gate delay involved to produce the output.
2. Static Timing Analysis (STA)
The Dynamic Timing Analysis has some disadvantages. It only checks the circuit functionality.
But the static timing analysis helps to find the time required for each gate to generate output.
But it fails to check whether the circuit produces correct output for given inputs.
Therefore, both analyses go hand in hand. One type verifies the time required to produce an
output whereas one verifies the result obtained is correct or not. However, this paper
concentrates on static timing analysis because that determines the circuit performance.
Delays in Combinational Circuit
1. Propagation Delay (Tp)
A transistor is the basic element in logic gate. It consumes some time to produce the output. For
example, in CMOS inverter (Fig3) when logic ‘1’ is applied at the input, output obtained is logic
‘0’. Similarly, logic ‘0’ at input results in logic ‘1’ at the output. Here, transistors consume time to
change their states which causes delay in generating the output. So, in general, time required to
produce output after the input is applied is called propagation delay. It can also be defined as
the time interval between change in input and change in output for any given circuit. Fig4
demonstrates the propagation delay for inverter.
Fig3. CMOS Inverter
The Dynamic Timing Analysis has some disadvantages. It only checks the circuit functionality.
But the static timing analysis helps to find the time required for each gate to generate output.
But it fails to check whether the circuit produces correct output for given inputs.
Therefore, both analyses go hand in hand. One type verifies the time required to produce an
output whereas one verifies the result obtained is correct or not. However, this paper
concentrates on static timing analysis because that determines the circuit performance.
Delays in Combinational Circuit
1. Propagation Delay (Tp)
A transistor is the basic element in logic gate. It consumes some time to produce the output. For
example, in CMOS inverter (Fig3) when logic ‘1’ is applied at the input, output obtained is logic
‘0’. Similarly, logic ‘0’ at input results in logic ‘1’ at the output. Here, transistors consume time to
change their states which causes delay in generating the output. So, in general, time required to
produce output after the input is applied is called propagation delay. It can also be defined as
the time interval between change in input and change in output for any given circuit. Fig4
demonstrates the propagation delay for inverter.
Fig3. CMOS Inverter
Fig4. Propagation Delay of Inverter
2. Tplh
The change in the input causes the output to change from low to high. This delay is called
propagation delay from low-to-high (Tplh). It is measured from input transition time (fifty
percent) till output rise time (fifty percent).
3. Tphl
The change in the input causes the output to change from high to low. This delay is called
propagation delay from high-to-low (Tphl). It is measured from input transition time (fifty
percent) till output fall time (fifty percent).
4. Rise Delay (Tr) and Fall Delay (Tf)
The time taken to change input or output from logic ‘0’ to logic ‘1’ is called rise delay. The time
taken for the circuit to change from logic ‘1’ to logic ‘0’ is called fall delay. The rise and fall
together is called transition delay.
Fig5. Rise and Fall Delay
2. Tplh
The change in the input causes the output to change from low to high. This delay is called
propagation delay from low-to-high (Tplh). It is measured from input transition time (fifty
percent) till output rise time (fifty percent).
3. Tphl
The change in the input causes the output to change from high to low. This delay is called
propagation delay from high-to-low (Tphl). It is measured from input transition time (fifty
percent) till output fall time (fifty percent).
4. Rise Delay (Tr) and Fall Delay (Tf)
The time taken to change input or output from logic ‘0’ to logic ‘1’ is called rise delay. The time
taken for the circuit to change from logic ‘1’ to logic ‘0’ is called fall delay. The rise and fall
together is called transition delay.
Fig5. Rise and Fall Delay
5. Interconnect (wire) Delay
Interconnect is the connection between two logic cells in the design. The signal consumes some
time to propagate through interconnect or wire. This delay is called interconnect delay.
6. Combinational Delay (Ld)
The combinational circuit consumes some time to produce the output. This delay is called the
combinational delay. The interconnect delay is included in the combinational delay.
Delays in Sequential Circuit
The flip-flops consume some time to produce the output. This is because the transistors consume time
to switch their states. The inverters and the transmission gates consume time to turn on and off which
introduces delay in producing the output.
Fig6. Transistor Level Circuit of Flip-Flop
The circuit shown in Fig6 is the flip-flop internal circuit diagram at transistor level. T1, T2, T3, T4 are the
transmission gates also called Pass gate or Pass switch. Pass gate is nothing but one PMOS and one
NMOS connected in parallel. Here, PMOS and NMOS turn on when logic ‘0’ and logic ‘1’ is applied to
PMOS and NMOS gates respectively.
Working of Flip-Flop
For example, T1 turns on when ‘clk’ = 1 and ‘clk_bar’ = 0. When T1 turns on, D input is reflected at point
‘M’ in the flip-flop. At that time, T2 and T3 pass gates are switched off because the controlling signal ‘clk’
is low for NMOS and ‘clk_bar ’ is high for PMOS. But T4 is switched on along with T1. Therefore, T4 just
latches the output ‘Q’ till it remains on.
Interconnect is the connection between two logic cells in the design. The signal consumes some
time to propagate through interconnect or wire. This delay is called interconnect delay.
6. Combinational Delay (Ld)
The combinational circuit consumes some time to produce the output. This delay is called the
combinational delay. The interconnect delay is included in the combinational delay.
Delays in Sequential Circuit
The flip-flops consume some time to produce the output. This is because the transistors consume time
to switch their states. The inverters and the transmission gates consume time to turn on and off which
introduces delay in producing the output.
Fig6. Transistor Level Circuit of Flip-Flop
The circuit shown in Fig6 is the flip-flop internal circuit diagram at transistor level. T1, T2, T3, T4 are the
transmission gates also called Pass gate or Pass switch. Pass gate is nothing but one PMOS and one
NMOS connected in parallel. Here, PMOS and NMOS turn on when logic ‘0’ and logic ‘1’ is applied to
PMOS and NMOS gates respectively.
Working of Flip-Flop
For example, T1 turns on when ‘clk’ = 1 and ‘clk_bar’ = 0. When T1 turns on, D input is reflected at point
‘M’ in the flip-flop. At that time, T2 and T3 pass gates are switched off because the controlling signal ‘clk’
is low for NMOS and ‘clk_bar ’ is high for PMOS. But T4 is switched on along with T1. Therefore, T4 just
latches the output ‘Q’ till it remains on.
When clk level is changed, i.e. ‘clk’ = 0 and ‘clk_bar’ = 1, T2 and T3 turns on and T1 and T4 are cutoff.
Therefore, T2 just latches the data present at ‘M’ whereas T3 launches the current data at ‘M’ to ‘Q’.
These events take place at two different clk levels forming the negative edge triggered flip-flop. Here, T1
and T2 together form master latch whereas T3 and T4 together form slave latch. The flip-flop internal
circuit diagram proves that the flip-flop consume time to launch the data. Therefore, the flip-flop timing
consideration is briefly discussed in the following section.
Flip-flop Timing Consideration
1. Setup Time (Ts)
The minimum time required for the data to become stable prior to the active clock edge is called
setup time. The pass gate ‘T1’ and inverters in master latch take some time to reflect input ‘D’ at
point ‘M’. This delay is referred flip-flop setup time.
2. Hold Time (Th)
The phenomenon in which the data should remain stable after the active clock edge is called
hold time. After the active edge has arrived, still T1 is on because transistors take some time to
turn off. Also, T2 start switching its state i.e. it turns on which holds the value at ‘M’. The T2 and
inverters introduce delay referred hold time.
Fig7. Setup Time and Hold Time
3. Setup Violation
According to setup time, it is mandatory that the data becomes stable prior the clock edge.
Suppose, if data changes within the setup time (shown in Fig8), then the circuit may enter into
metastable state. This phenomenon is called setup violation.
4. Hold Violation
According to hold time, the data should remain stable for some time after the active clock edge.
Suppose the data transition occurs within the hold time (shown in Fig8), then the circuit enters
in metastable state. This is called hold violation.
Therefore, T2 just latches the data present at ‘M’ whereas T3 launches the current data at ‘M’ to ‘Q’.
These events take place at two different clk levels forming the negative edge triggered flip-flop. Here, T1
and T2 together form master latch whereas T3 and T4 together form slave latch. The flip-flop internal
circuit diagram proves that the flip-flop consume time to launch the data. Therefore, the flip-flop timing
consideration is briefly discussed in the following section.
Flip-flop Timing Consideration
1. Setup Time (Ts)
The minimum time required for the data to become stable prior to the active clock edge is called
setup time. The pass gate ‘T1’ and inverters in master latch take some time to reflect input ‘D’ at
point ‘M’. This delay is referred flip-flop setup time.
2. Hold Time (Th)
The phenomenon in which the data should remain stable after the active clock edge is called
hold time. After the active edge has arrived, still T1 is on because transistors take some time to
turn off. Also, T2 start switching its state i.e. it turns on which holds the value at ‘M’. The T2 and
inverters introduce delay referred hold time.
Fig7. Setup Time and Hold Time
3. Setup Violation
According to setup time, it is mandatory that the data becomes stable prior the clock edge.
Suppose, if data changes within the setup time (shown in Fig8), then the circuit may enter into
metastable state. This phenomenon is called setup violation.
4. Hold Violation
According to hold time, the data should remain stable for some time after the active clock edge.
Suppose the data transition occurs within the hold time (shown in Fig8), then the circuit enters
in metastable state. This is called hold violation.
Fig8. Setup and Hold Violation
5. Metastable State
In metastable state, the output keeps dangling between logic 1 and logic 0 for unbounded time
period. For example, consider the data transition taking place within the restricted region or
near the active clock edge. At that time, T1 and T2 start changing their states and even the point
‘M’ also starts transition. But before T1 can capture the data, the input is cutoff (T1 is turned off)
which results in voltage at ‘M’ lying between logic ‘1’ and logic ‘0’. After the clock level makes
transition, T3 turns on, this transmit the voltage at ‘M’ to flip-flop output ‘Q’. Therefore, the
output obtained is between ‘0’ and ‘1’. This phenomenon is called metastability.
6. Clock to Output time (Tc-q)
The minimum time required to launch data after the clock arrives is called clock to output time.
Here, T3 and inverters consume time to launch the data at the output ‘Q’. This is nothing but the
flip-flop slave delay.
7. Skew (Tskew)
The Phase Locked Loop (PLL) causes the clock edge to arrive early or late than expected. For
example, assume the clock edge should arrive at 5ns. Due to some internal problems in PLL the
clock edge arrives at 4.95 ns or 5.05 ns (as shown in Fig9). The difference between actual arrival
time and the expected arrival time is called skew. The following diagram demonstrates the skew
in the circuit.
5. Metastable State
In metastable state, the output keeps dangling between logic 1 and logic 0 for unbounded time
period. For example, consider the data transition taking place within the restricted region or
near the active clock edge. At that time, T1 and T2 start changing their states and even the point
‘M’ also starts transition. But before T1 can capture the data, the input is cutoff (T1 is turned off)
which results in voltage at ‘M’ lying between logic ‘1’ and logic ‘0’. After the clock level makes
transition, T3 turns on, this transmit the voltage at ‘M’ to flip-flop output ‘Q’. Therefore, the
output obtained is between ‘0’ and ‘1’. This phenomenon is called metastability.
6. Clock to Output time (Tc-q)
The minimum time required to launch data after the clock arrives is called clock to output time.
Here, T3 and inverters consume time to launch the data at the output ‘Q’. This is nothing but the
flip-flop slave delay.
7. Skew (Tskew)
The Phase Locked Loop (PLL) causes the clock edge to arrive early or late than expected. For
example, assume the clock edge should arrive at 5ns. Due to some internal problems in PLL the
clock edge arrives at 4.95 ns or 5.05 ns (as shown in Fig9). The difference between actual arrival
time and the expected arrival time is called skew. The following diagram demonstrates the skew
in the circuit.
Fig9. Skew
Positive skew and Negative skew
The clock edge arrives at the time instant after the expected arrival time. The time interval
between the arrival times is positive skew. The clock edge arrives at the time instant before the
expected arrival time. The time interval between the arrival times is negative skew.
The skew plays a negative role in causing hold violation or setup violation in the circuit. The above
discussed timing parameters play a significant role in determining the circuit performance. Therefore,
this discussion paves a way to timing analysis part.
Positive skew and Negative skew
The clock edge arrives at the time instant after the expected arrival time. The time interval
between the arrival times is positive skew. The clock edge arrives at the time instant before the
expected arrival time. The time interval between the arrival times is negative skew.
The skew plays a negative role in causing hold violation or setup violation in the circuit. The above
discussed timing parameters play a significant role in determining the circuit performance. Therefore,
this discussion paves a way to timing analysis part.
Timing Analysis
To perform timing analysis in given circuit, it is important to understand the timing paths present in the
circuit. The following circuit diagram shows the timing paths in the sequential circuit (Fig10). The
combinational path between any two flip-flops is reg-to-reg path. The path from chip input till the first
flip-flop input is called input-to-reg path. The path from flip-flop till the circuit output is called reg-to-
output path. The combinational part excluding the registers in the circuit is called input-to-output path.
Fig10. Different types of paths in the circuit
The static timing analysis is divided into two major types i.e. Setup Timing Analysis and Hold Timing
Analysis. The setup time analysis deals with the critical path (long path) in the circuit because the critical
path determines the clock frequency. Instead, the hold analysis deals with the minimum path in the
circuit as the minimum path is responsible for the race condition. Before discussing the timing analysis,
it is important to understand the delay calculation along different paths in the combinational block. It
helps in identifying the short and long path in the circuit. The following section briefly describes the logic
delay calculation along the path.
To perform timing analysis in given circuit, it is important to understand the timing paths present in the
circuit. The following circuit diagram shows the timing paths in the sequential circuit (Fig10). The
combinational path between any two flip-flops is reg-to-reg path. The path from chip input till the first
flip-flop input is called input-to-reg path. The path from flip-flop till the circuit output is called reg-to-
output path. The combinational part excluding the registers in the circuit is called input-to-output path.
Fig10. Different types of paths in the circuit
The static timing analysis is divided into two major types i.e. Setup Timing Analysis and Hold Timing
Analysis. The setup time analysis deals with the critical path (long path) in the circuit because the critical
path determines the clock frequency. Instead, the hold analysis deals with the minimum path in the
circuit as the minimum path is responsible for the race condition. Before discussing the timing analysis,
it is important to understand the delay calculation along different paths in the combinational block. It
helps in identifying the short and long path in the circuit. The following section briefly describes the logic
delay calculation along the path.
Calculation of Delay in combinational paths
Fig11. Calculation of Long path and short path
In order to identify the critical path and the shortest path between two flip-flops, it is necessary to
compute the total logic delay for each path in the circuit. As a running example, consider the circuit
given in Fig11. In Fig11, all interconnect (wire) and NAND gate delays are specified. For example, at Input
‘B’, 0.1 is the minimum delay required for the input to arrive whereas 0.5 is the maximum delay required
for input B to arrive at the NAND gate ‘N1’ input. Similarly, for NAND gate ‘N1’, 0.5 is the minimum delay
and 0.9 is the maximum delay. Similarly, the NAND gates and interconnect delays are specified in the
circuit. The next section demonstrates delay calculation for all paths in the circuit.
Calculating delay of longest path
Path 1
Max delay (Input A + N2 + N4) = 0.8 + 0.9 + 0.4 + 0.8 = 2.9
Path 2
Max delay (Input B + N1 + N2 + N4) = 0.5 + 0.9 + 0.5 + 0.9 + 0.4 + 0.8 = 4.0
Path 3
Max delay (Input B + N1 + N3 + N4) = 0.5 + 0.9 + 0.3 + 0.8 + 0.3 + 0.8 = 3.6
Path 4
Max delay (Input C + N1 + N2 + N4) = 0.6 + 0.9 + 0.5 + 0.9 + 0.4 + 0.8 = 4.1
Path 5
Max delay (Input C + N1 + N3 + N4) = 0.6 + 0.9 + 0.3 + 0.8 + 0.3 + 0.8 = 3.7
Path 6
Max delay (Input D + N3 + N4) = 0.4 + 0.8 + 0.3 + 0.8 = 2.3
Fig11. Calculation of Long path and short path
In order to identify the critical path and the shortest path between two flip-flops, it is necessary to
compute the total logic delay for each path in the circuit. As a running example, consider the circuit
given in Fig11. In Fig11, all interconnect (wire) and NAND gate delays are specified. For example, at Input
‘B’, 0.1 is the minimum delay required for the input to arrive whereas 0.5 is the maximum delay required
for input B to arrive at the NAND gate ‘N1’ input. Similarly, for NAND gate ‘N1’, 0.5 is the minimum delay
and 0.9 is the maximum delay. Similarly, the NAND gates and interconnect delays are specified in the
circuit. The next section demonstrates delay calculation for all paths in the circuit.
Calculating delay of longest path
Path 1
Max delay (Input A + N2 + N4) = 0.8 + 0.9 + 0.4 + 0.8 = 2.9
Path 2
Max delay (Input B + N1 + N2 + N4) = 0.5 + 0.9 + 0.5 + 0.9 + 0.4 + 0.8 = 4.0
Path 3
Max delay (Input B + N1 + N3 + N4) = 0.5 + 0.9 + 0.3 + 0.8 + 0.3 + 0.8 = 3.6
Path 4
Max delay (Input C + N1 + N2 + N4) = 0.6 + 0.9 + 0.5 + 0.9 + 0.4 + 0.8 = 4.1
Path 5
Max delay (Input C + N1 + N3 + N4) = 0.6 + 0.9 + 0.3 + 0.8 + 0.3 + 0.8 = 3.7
Path 6
Max delay (Input D + N3 + N4) = 0.4 + 0.8 + 0.3 + 0.8 = 2.3
Comparing all the maximum paths in the circuit, path 4 has the maximum delay and therefore it is
responsible for determining the clock frequency (explained later). Similarly, the minimum delay along
the path in the combinational circuit can be calculated. The only difference in calculating maximum path
and minimum path is, while calculating minimum delay, consider the minimum values for all
interconnects and the NAND gates along the path. The path with the least delay is responsible for race
condition (explained in hold analysis).
Minimum path in the circuit
Path 1
Min delay (Input A + N2 + N4) = 0.2 + 0.4 + 0.2 + 0.5 = 1.3
Path 2
Min delay (Input D + N3 + N4) = 0.2 + 0.6 + 0.1 + 0.5 = 1.4
Similarly, compute minimum delays along the path, the shortest path obtained possess 1.3 as the least
delay. Other paths possess delay greater than 1.3 and so the path from Input ‘A’ till output ‘Y’ is the
shortest path and is considered for hold calculation. Now the combinational logic delay between two
flip-flops can be computed. So, the next section describes the reg-to-reg path timing analysis.
responsible for determining the clock frequency (explained later). Similarly, the minimum delay along
the path in the combinational circuit can be calculated. The only difference in calculating maximum path
and minimum path is, while calculating minimum delay, consider the minimum values for all
interconnects and the NAND gates along the path. The path with the least delay is responsible for race
condition (explained in hold analysis).
Minimum path in the circuit
Path 1
Min delay (Input A + N2 + N4) = 0.2 + 0.4 + 0.2 + 0.5 = 1.3
Path 2
Min delay (Input D + N3 + N4) = 0.2 + 0.6 + 0.1 + 0.5 = 1.4
Similarly, compute minimum delays along the path, the shortest path obtained possess 1.3 as the least
delay. Other paths possess delay greater than 1.3 and so the path from Input ‘A’ till output ‘Y’ is the
shortest path and is considered for hold calculation. Now the combinational logic delay between two
flip-flops can be computed. So, the next section describes the reg-to-reg path timing analysis.
Setup Timing Analysis
Fig12. Setup and Hold Analysis Circuit
The setup timing analysis deals with the critical path (long path) in the circuit because the long path
determines the clock frequency. If the clock frequency is higher, the output is produced at a faster rate.
Therefore, the logic delay has to be as small as possible. Therefore, the setup condition in equation (1)
determines the clock time period. According to the condition, the clock period should be greater than
the logic delay, setup time and skew.
Tclk > Tc-q + Ld + Ts + 2Tskew (1)
The above equation says the critical path includes ‘Tc-q’ as launch flip-flop (Flip-flop that launches data
in the circuit) consumes some time to produce the output. The ‘Ld’ represents the logic delay between
launch and capture flip-flops. ‘Ts’ is the setup time and ‘Tskew’ is the clock skew. ‘Tclk’ is the clock
period.
In Fig9, two combinational paths introduce delay. The first path is inverter delay plus AND gate delay
which is about 3ns. The second path is only AND gate which possess 2ns delay. The maximum path has 3
ns delay and hence it is considered in the setup condition. Substitute the values in equation (1) that are
given in Fig12.
5 > 1+3+2+2
5 > 9
Fig12. Setup and Hold Analysis Circuit
The setup timing analysis deals with the critical path (long path) in the circuit because the long path
determines the clock frequency. If the clock frequency is higher, the output is produced at a faster rate.
Therefore, the logic delay has to be as small as possible. Therefore, the setup condition in equation (1)
determines the clock time period. According to the condition, the clock period should be greater than
the logic delay, setup time and skew.
Tclk > Tc-q + Ld + Ts + 2Tskew (1)
The above equation says the critical path includes ‘Tc-q’ as launch flip-flop (Flip-flop that launches data
in the circuit) consumes some time to produce the output. The ‘Ld’ represents the logic delay between
launch and capture flip-flops. ‘Ts’ is the setup time and ‘Tskew’ is the clock skew. ‘Tclk’ is the clock
period.
In Fig9, two combinational paths introduce delay. The first path is inverter delay plus AND gate delay
which is about 3ns. The second path is only AND gate which possess 2ns delay. The maximum path has 3
ns delay and hence it is considered in the setup condition. Substitute the values in equation (1) that are
given in Fig12.
5 > 1+3+2+2
5 > 9
The above condition proves that the circuit in Fig12 cannot work at 5ns clock. This condition is called
setup violation and consequently may enter in metastable state. The clock period should be minimum
9ns to avoid setup violation. Therefore, to decrease the clock period (increase clock frequency) the logic
delay between two flip-flops has to be reduced.
Hold Timing Analysis
Hold analysis is exactly opposite of setup analysis. This type concentrates on short path in the circuit.
The short path is responsible for the race condition which results in undesirable output. Consider the
same circuit shown in Fig9 the short path has 2ns delay. The hold condition is given as follows
Th + 2Tskew < Tc-q + Ld (II)
2+2 < 1 + 2
4 < 3
According to the condition, the short path should be greater than hold and skew. But above relation is
proved wrong which states the circuit can race. This phenomenon is called hold violation. Therefore, the
output obtained is undesirable. In order to avoid hold violation, the minimum logic delay should be
greater than hold time and skew.
Race Condition
Fig13. Race Condition
Race condition is the phenomenon in which the output is obtained after the first clock edge instead of
second edge. For example, consider the circuit in Fig13, the logic delay is zero between launch and
capture flip-flops. In this situation, the capture flip-flop output is obtained directly after the first edge
instead of second edge.
setup violation and consequently may enter in metastable state. The clock period should be minimum
9ns to avoid setup violation. Therefore, to decrease the clock period (increase clock frequency) the logic
delay between two flip-flops has to be reduced.
Hold Timing Analysis
Hold analysis is exactly opposite of setup analysis. This type concentrates on short path in the circuit.
The short path is responsible for the race condition which results in undesirable output. Consider the
same circuit shown in Fig9 the short path has 2ns delay. The hold condition is given as follows
Th + 2Tskew < Tc-q + Ld (II)
2+2 < 1 + 2
4 < 3
According to the condition, the short path should be greater than hold and skew. But above relation is
proved wrong which states the circuit can race. This phenomenon is called hold violation. Therefore, the
output obtained is undesirable. In order to avoid hold violation, the minimum logic delay should be
greater than hold time and skew.
Race Condition
Fig13. Race Condition
Race condition is the phenomenon in which the output is obtained after the first clock edge instead of
second edge. For example, consider the circuit in Fig13, the logic delay is zero between launch and
capture flip-flops. In this situation, the capture flip-flop output is obtained directly after the first edge
instead of second edge.
The analysis is the most important one as maximum chips possess typical reg-to-reg path and analysis is
done as discussed above. But chips also contain different paths that require analysis. For example, the
other paths in the circuit like input-to-reg, reg-to-output and input-to-output also need timing analysis.
The further section describes timing analysis for all these paths.
Input-To-Reg Path
Fig14. Input-to-Reg Path
The circuit in Fig14 is an input-to-reg path. The input can reach capture flip-flop at random time. If the
timing analysis for this path is not performed then the circuit may enter into metastable state. So, it is
important to perform static timing analysis for this path. The important thing to note is there is no
launch flip-flop present in the circuit. Before commencing with timing analysis it is important to
understand few terms.
Virtual Flip-flop
In reg-to-reg path, actual flip-flop launches the data. In input-to-reg path, the input flip-flop is absent.
Therefore, connect a virtual flip-flop (shown with dotted lines in Fig12) at the circuit input. Virtual flip-
flop does not introduce delay in launching the data therefore it has zero ‘Tc-q’ delay.
Virtual Clock
The clock edges control flip-flops, therefore it is crucial to connect the clock to a virtual flip-flop (shown
in Fig15) called virtual clock. The virtual clock does not introduce delay because it does not exist
physically. As shown in the Fig15, L1 is the virtual clock triggering virtual launch flip-flop whereas L2 is
the actual clock triggering capture flip-flop.
done as discussed above. But chips also contain different paths that require analysis. For example, the
other paths in the circuit like input-to-reg, reg-to-output and input-to-output also need timing analysis.
The further section describes timing analysis for all these paths.
Input-To-Reg Path
Fig14. Input-to-Reg Path
The circuit in Fig14 is an input-to-reg path. The input can reach capture flip-flop at random time. If the
timing analysis for this path is not performed then the circuit may enter into metastable state. So, it is
important to perform static timing analysis for this path. The important thing to note is there is no
launch flip-flop present in the circuit. Before commencing with timing analysis it is important to
understand few terms.
Virtual Flip-flop
In reg-to-reg path, actual flip-flop launches the data. In input-to-reg path, the input flip-flop is absent.
Therefore, connect a virtual flip-flop (shown with dotted lines in Fig12) at the circuit input. Virtual flip-
flop does not introduce delay in launching the data therefore it has zero ‘Tc-q’ delay.
Virtual Clock
The clock edges control flip-flops, therefore it is crucial to connect the clock to a virtual flip-flop (shown
in Fig15) called virtual clock. The virtual clock does not introduce delay because it does not exist
physically. As shown in the Fig15, L1 is the virtual clock triggering virtual launch flip-flop whereas L2 is
the actual clock triggering capture flip-flop.
Fig15. Input-to-Reg Path Analysis
Setup Analysis for this path
The virtual clock and virtual flip-flop converts the input-to-reg path into basic reg-to-reg path. Therefore
the input-to-output path timing analysis is similar to reg-to-reg path. The difference between these two
path is the clock-to-output ‘Tc-q’ is absent because the launch flip-flop is virtual. Since virtual clock is
applied at launch flip-flop, therefore the launch flip-flop skew is not considered in the setup condition.
To avoid setup violation at the chip input, the clock time period should be greater than logic delay,
capture flip-flop setup time and half skew. Therefore, the input-to-reg path setup condition for is shown
in equation (3).
Tclk > Ld + Ts (capture flop) + Tskew (3)
Hold Analysis
Typically, the hold analysis is performed for both flip-flops in reg-to-reg path. In an input-to-reg path the
launch flip-flop is absent therefore the capture flip-flop is considered in hold analysis. The inputs can
arrive at anytime which may cause capture flip-flop to race. For example, the circuit shown in Fig16
below demonstrates the race condition.
Th + Tskew < Ld
2 + 1 < 2
3 < 2
The hold condition for input-to-reg path is that the logic delay is less than hold time and skew. In the
given hold condition, the Tc-q is absent as well as the Tskew is halved because the input flip-flop is
absent in the circuit. As per the given values in the circuit, the hold condition is violated for input-to-reg
path. Therefore, it is extremely essential to perform hold analysis for this path in order to avoid race
condition at chip input.
Setup Analysis for this path
The virtual clock and virtual flip-flop converts the input-to-reg path into basic reg-to-reg path. Therefore
the input-to-output path timing analysis is similar to reg-to-reg path. The difference between these two
path is the clock-to-output ‘Tc-q’ is absent because the launch flip-flop is virtual. Since virtual clock is
applied at launch flip-flop, therefore the launch flip-flop skew is not considered in the setup condition.
To avoid setup violation at the chip input, the clock time period should be greater than logic delay,
capture flip-flop setup time and half skew. Therefore, the input-to-reg path setup condition for is shown
in equation (3).
Tclk > Ld + Ts (capture flop) + Tskew (3)
Hold Analysis
Typically, the hold analysis is performed for both flip-flops in reg-to-reg path. In an input-to-reg path the
launch flip-flop is absent therefore the capture flip-flop is considered in hold analysis. The inputs can
arrive at anytime which may cause capture flip-flop to race. For example, the circuit shown in Fig16
below demonstrates the race condition.
Th + Tskew < Ld
2 + 1 < 2
3 < 2
The hold condition for input-to-reg path is that the logic delay is less than hold time and skew. In the
given hold condition, the Tc-q is absent as well as the Tskew is halved because the input flip-flop is
absent in the circuit. As per the given values in the circuit, the hold condition is violated for input-to-reg
path. Therefore, it is extremely essential to perform hold analysis for this path in order to avoid race
condition at chip input.
Fig16. Input-to-reg path circuit example
Reg-to-Output Path
Similarly, the output flip-flop (reg) may launch data which is the chip output called as reg-to-output
path. At the chip output no capture flip-flop is present which can capture the data (shown in Fig17). To
perform reg-to-output path timing analysis, connect the virtual flip-flop and virtual clock at the chip
output (shown in dotted lines in Fig 17).
Fig17. Reg-to-Output path Analysis
Tclk > Tc-q + Ld + Tskew (4)
The virtual flip-flop is present at the output. Therefore, the capture flip-flop setup time is not considered
in the setup condition because virtual flip-flop does not introduce delay. Here, L1 is the real clock and L2
is the virtual clock. As a result, L2 does not introduce skew. Therefore, the skew is halved because virtual
Reg-to-Output Path
Similarly, the output flip-flop (reg) may launch data which is the chip output called as reg-to-output
path. At the chip output no capture flip-flop is present which can capture the data (shown in Fig17). To
perform reg-to-output path timing analysis, connect the virtual flip-flop and virtual clock at the chip
output (shown in dotted lines in Fig 17).
Fig17. Reg-to-Output path Analysis
Tclk > Tc-q + Ld + Tskew (4)
The virtual flip-flop is present at the output. Therefore, the capture flip-flop setup time is not considered
in the setup condition because virtual flip-flop does not introduce delay. Here, L1 is the real clock and L2
is the virtual clock. As a result, L2 does not introduce skew. Therefore, the skew is halved because virtual
clock is given to the virtual flip-flop. Therefore, the reg-to-output path setup analysis is performed using
equation (4).
Hold Analysis for reg-to-output path
The input flip-flop introduces slave delay in the data path. Therefore, the data should remain stable at
least for flip-flop hold time. Also, clock at the launch flip-flop may introduce skew and therefore, skew is
considered in the hold condition. Therefore, the reg-to-output path hold condition says the flip-flop hold
time and skew should be less than clock-to-output delay and logic delay along the short path. Therefore,
the hold condition is given in equation (5).
Th + Tskew < Tc-q + Ld (5)
Comparing equation (2) and (5), the skew is halved because the virtual clock does not introduce any
variation in the clock path. This discussion proves the timing analysis of reg-to-output path needs to be
performed to avoid metastability and race condition. The next analysis is for input-to-output path
discussed briefly in the following section.
Input-to-Output Path
The design can have a path going from input port to output port. So, flip-flop is absent at input or output
end for this path. So, timing analysis is performed in a similar way as explained for input-to-reg path and
reg-to-output path. Since no flip-flops are present either at input or output port, connect virtual flip-
flops at both ends.
Fig18. Input-to-Reg Path analysis
The circuit with virtual flip-flops is shown in Fig18. Here, both launch flip-flop and capture flip-flop is
virtual and therefore the setup condition is given in equation (6). Comparing equation (1) and (6), only
logic delay is included because the virtual flip-flops do not introduce any delay in the data path.
Tclk > Ld (6)
equation (4).
Hold Analysis for reg-to-output path
The input flip-flop introduces slave delay in the data path. Therefore, the data should remain stable at
least for flip-flop hold time. Also, clock at the launch flip-flop may introduce skew and therefore, skew is
considered in the hold condition. Therefore, the reg-to-output path hold condition says the flip-flop hold
time and skew should be less than clock-to-output delay and logic delay along the short path. Therefore,
the hold condition is given in equation (5).
Th + Tskew < Tc-q + Ld (5)
Comparing equation (2) and (5), the skew is halved because the virtual clock does not introduce any
variation in the clock path. This discussion proves the timing analysis of reg-to-output path needs to be
performed to avoid metastability and race condition. The next analysis is for input-to-output path
discussed briefly in the following section.
Input-to-Output Path
The design can have a path going from input port to output port. So, flip-flop is absent at input or output
end for this path. So, timing analysis is performed in a similar way as explained for input-to-reg path and
reg-to-output path. Since no flip-flops are present either at input or output port, connect virtual flip-
flops at both ends.
Fig18. Input-to-Reg Path analysis
The circuit with virtual flip-flops is shown in Fig18. Here, both launch flip-flop and capture flip-flop is
virtual and therefore the setup condition is given in equation (6). Comparing equation (1) and (6), only
logic delay is included because the virtual flip-flops do not introduce any delay in the data path.
Tclk > Ld (6)
Hold Time check for input-to-output path
Th < Ld (7)
Comparing equation (2) and (7), the Tc-q and Tskew delay are removed because the virtual flip-flops do
not introduce slave delay in the data path. Therefore, the hold condition for input-to-output path only
depends on logic delay and is given in equation (7). The above analysis explains the basic paths among
all different timing analysis. The following example demonstrates how to perform timing analysis for
different paths in the circuit.
Fig19. Timing Analysis Example
The different timing paths like reg-to-reg, input-to-reg, reg-to-output and input-to-output are present in
the circuit shown in Fig19. Therefore, the setup and hold analysis is performed for all these paths
present in the circuit. Therefore, the next section describes the setup and hold analysis for the circuit in
Fig19.
Setup Analysis
The setup analysis deals with the maximum delay in the circuit. According to the setup condition, the
combinational path with maximum delay determines the clock frequency. Therefore, the timing paths
available in Fig15 are reg-to-reg path that includes U1 – U4 – U2 and U2 – U3 – U1. The input-to-reg
includes U7 – U4 – U2 and U7 – U3 – U1. Also, U1 – U5 – U6 and U2 – U5 – U6 are reg-to-output path in
the circuit. The path U7 – U5 – U6 is input-to-output path. Amongst all these data paths, the path with
maximum delay determines the clock frequency. The clock path includes U8 – U1 and U8 – U2.
For paths other than reg-to-reg, use the setup conditions as discussed in respective sections. To perform
setup analysis, consider the maximum delay along all paths. For example, the delay along reg-to-reg is
calculated using the relation Tc-q + Ld + 2*Tskew + Ts. Therefore, the maximum delay is 12ns along U1 –
U4 – U2 path and 13ns along U2 – U3 – U1 path.
Th < Ld (7)
Comparing equation (2) and (7), the Tc-q and Tskew delay are removed because the virtual flip-flops do
not introduce slave delay in the data path. Therefore, the hold condition for input-to-output path only
depends on logic delay and is given in equation (7). The above analysis explains the basic paths among
all different timing analysis. The following example demonstrates how to perform timing analysis for
different paths in the circuit.
Fig19. Timing Analysis Example
The different timing paths like reg-to-reg, input-to-reg, reg-to-output and input-to-output are present in
the circuit shown in Fig19. Therefore, the setup and hold analysis is performed for all these paths
present in the circuit. Therefore, the next section describes the setup and hold analysis for the circuit in
Fig19.
Setup Analysis
The setup analysis deals with the maximum delay in the circuit. According to the setup condition, the
combinational path with maximum delay determines the clock frequency. Therefore, the timing paths
available in Fig15 are reg-to-reg path that includes U1 – U4 – U2 and U2 – U3 – U1. The input-to-reg
includes U7 – U4 – U2 and U7 – U3 – U1. Also, U1 – U5 – U6 and U2 – U5 – U6 are reg-to-output path in
the circuit. The path U7 – U5 – U6 is input-to-output path. Amongst all these data paths, the path with
maximum delay determines the clock frequency. The clock path includes U8 – U1 and U8 – U2.
For paths other than reg-to-reg, use the setup conditions as discussed in respective sections. To perform
setup analysis, consider the maximum delay along all paths. For example, the delay along reg-to-reg is
calculated using the relation Tc-q + Ld + 2*Tskew + Ts. Therefore, the maximum delay is 12ns along U1 –
U4 – U2 path and 13ns along U2 – U3 – U1 path.
Similarly, the input-to-reg path delay is computed using the relation Ld + Tskew + Ts. Here the Tc-q is
absent as well as Tskew is halved because the input launch flip-flop is absent. Still, this path is
considered because that can cause setup violation. Therefore, the maximum path delay is 11ns along U7
– U4 – U2 path and 12ns along U7 – U3 – U1 path.
The reg-to-output path delay is calculated using the relation Tc-q + Ld + Tskew. Here, the output capture
flip-flop is absent. Therefore, the setup time is not considered and skew is also halved. So, the maximum
path delay is 17ns for U1 – U5 – U6 path and U2 – U5 – U6 path respectively. In input-to-output path,
the launch and capture flip-flops are absent and therefore logic delay (Ld) determines the maximum
delay along the path U7 – U5 – U6.
C.T > 17ns
The maximum delay obtained is 17ns after comparing maximum path delays in the circuit. Therefore, to
avoid setup violation, the clock time period should be greater than 17ns. The above analysis is
performed to avoid circuit failure due to long path in the circuit. Similarly, the circuit may fail due to
short path called hold violation. Therefore, it is extremely essential to perform hold analysis to avoid
race condition in the circuit. The next section describes briefly about hold analysis for the given circuit.
Hold Analysis
The hold check deals with the minimum path in the circuit because the minimum path (short path) can
cause race condition. Therefore, the different paths hold condition is described in the respective
sections. To perform hold analysis, the minimum delay along various paths is considered.
Solving the example in Fig15, consider all the paths for hold analysis. For example, in reg-to-reg path U1
– U4 – U2, the hold condition is checked using the relation Th + 2*Tskew < Tc-q + Ld. Similarly, all reg-to-
reg paths hold condition is checked using the relation given below.
Th + 2*Tskew < Tc-q + Ld (8)
2 + 2 < 1 + 7
4 < 8
Th + Tskew < Ld (9)
2 + 1 < 8
3<8
Similarly for input-to-reg path U7 – U4 – U2, the hold condition is given in equation (9). Therefore, the
input-to-reg path hold analysis is performed using the equation (9). Along with other paths, hold is also
checked for reg-to-output path. The condition for this path is given in equation (10).
absent as well as Tskew is halved because the input launch flip-flop is absent. Still, this path is
considered because that can cause setup violation. Therefore, the maximum path delay is 11ns along U7
– U4 – U2 path and 12ns along U7 – U3 – U1 path.
The reg-to-output path delay is calculated using the relation Tc-q + Ld + Tskew. Here, the output capture
flip-flop is absent. Therefore, the setup time is not considered and skew is also halved. So, the maximum
path delay is 17ns for U1 – U5 – U6 path and U2 – U5 – U6 path respectively. In input-to-output path,
the launch and capture flip-flops are absent and therefore logic delay (Ld) determines the maximum
delay along the path U7 – U5 – U6.
C.T > 17ns
The maximum delay obtained is 17ns after comparing maximum path delays in the circuit. Therefore, to
avoid setup violation, the clock time period should be greater than 17ns. The above analysis is
performed to avoid circuit failure due to long path in the circuit. Similarly, the circuit may fail due to
short path called hold violation. Therefore, it is extremely essential to perform hold analysis to avoid
race condition in the circuit. The next section describes briefly about hold analysis for the given circuit.
Hold Analysis
The hold check deals with the minimum path in the circuit because the minimum path (short path) can
cause race condition. Therefore, the different paths hold condition is described in the respective
sections. To perform hold analysis, the minimum delay along various paths is considered.
Solving the example in Fig15, consider all the paths for hold analysis. For example, in reg-to-reg path U1
– U4 – U2, the hold condition is checked using the relation Th + 2*Tskew < Tc-q + Ld. Similarly, all reg-to-
reg paths hold condition is checked using the relation given below.
Th + 2*Tskew < Tc-q + Ld (8)
2 + 2 < 1 + 7
4 < 8
Th + Tskew < Ld (9)
2 + 1 < 8
3<8
Similarly for input-to-reg path U7 – U4 – U2, the hold condition is given in equation (9). Therefore, the
input-to-reg path hold analysis is performed using the equation (9). Along with other paths, hold is also
checked for reg-to-output path. The condition for this path is given in equation (10).
Th + Tskew < Tc-q + Ld (10)
2 + 1 < 1 + 15
3 < 16
Th < Ld (11)
2 < 1 + 9 + 6
2 < 16
Similarly, the input-to-output path is checked using the condition given in equation (11). Therefore, the
above analysis proves there is no hold violation for any path in the circuit. It is extremely important to
perform hold analysis beforehand because it is difficult to solve hold violation in physical design stage.
The above example demonstrates solving timing problem involves paths other than reg-to-reg path in
the circuit. Different timing checks involved in the circuit along with the discussed above are explained
briefly in this paper. Along with those paths, clock gating check, recovery and removal timing check, half
cycle check and many more are explained in this paper. Consider the circuit in Fig20 which shows signals
like reset, enable and asynchronous data signals that may cause setup and hold violation. Therefore, it is
essential to solve timing violation for these paths as well. Therefore, the next sections deal with all these
different timing checks.
Fig20. Circuit for Different Types of Timing Checks
The circuit shown in Fig20 possesses many different paths along with reg-to-reg path, input-to-reg path,
reg-to-output path and input-to-output path. For example, the path from ‘another_clk’ to ‘gating signal’
to ‘flip-flop clock pin’ is a clock gating path. Also, the path from ‘clock buffer’ to ‘latch’ to flip-flop output
signal ‘out1’ requires timing check. Therefore, many such paths available in the practical circuit are
shown in Fig20. These paths may cause setup violation or hold violation and so it is extremely essential
to perform timing analysis for all these paths as well. Therefore, the following sections describe timing
checks for different paths in the circuit.
2 + 1 < 1 + 15
3 < 16
Th < Ld (11)
2 < 1 + 9 + 6
2 < 16
Similarly, the input-to-output path is checked using the condition given in equation (11). Therefore, the
above analysis proves there is no hold violation for any path in the circuit. It is extremely important to
perform hold analysis beforehand because it is difficult to solve hold violation in physical design stage.
The above example demonstrates solving timing problem involves paths other than reg-to-reg path in
the circuit. Different timing checks involved in the circuit along with the discussed above are explained
briefly in this paper. Along with those paths, clock gating check, recovery and removal timing check, half
cycle check and many more are explained in this paper. Consider the circuit in Fig20 which shows signals
like reset, enable and asynchronous data signals that may cause setup and hold violation. Therefore, it is
essential to solve timing violation for these paths as well. Therefore, the next sections deal with all these
different timing checks.
Fig20. Circuit for Different Types of Timing Checks
The circuit shown in Fig20 possesses many different paths along with reg-to-reg path, input-to-reg path,
reg-to-output path and input-to-output path. For example, the path from ‘another_clk’ to ‘gating signal’
to ‘flip-flop clock pin’ is a clock gating path. Also, the path from ‘clock buffer’ to ‘latch’ to flip-flop output
signal ‘out1’ requires timing check. Therefore, many such paths available in the practical circuit are
shown in Fig20. These paths may cause setup violation or hold violation and so it is extremely essential
to perform timing analysis for all these paths as well. Therefore, the following sections describe timing
checks for different paths in the circuit.
Clock gating check
A clock gating check is required when a gating signal controls the clock signal path in a logic circuit.
Consider the simplified gated clock circuit diagram shown in Fig21. The AND gate has two inputs which
includes clock signal and ‘enable’ signal also called gated signal. The AND gate output is called ‘gated
clock’.
Fig21. Clock Gating Circuit
Prior to clock gating check, few conditions must be considered. The gated clock is used to drive flip-flops
and helps to generate new clock. The generated clock means the clock which has different parameters
like phase difference, frequency change as compared to original clock (system clock). Another condition
is for gated signal. The gated signal should not be used as a clock to drive any flip-flops in the circuit. The
gated and clock signal can be connected to AND gate, OR gate or any logic that exhibits ‘AND’ function
or ‘OR’ function. It means clock gating signal is divided into two types.
Active-high clock gating signal and Active-low clock gating signal
Active-high clock gating signal occurs when logic circuit has ‘AND’ or ‘NAND’ function. The clock is
allowed to propagate through gated logic when the gated signal is active high otherwise the clock is
ceased to propagate when gated signal is active low. Similarly, the active-low clock gating signal occurs
when logic circuit has ‘OR’ or ‘NOR’ function. Here, when the gated signal is active low, then only clock
can propagate through the logic circuit.
Consider for example, the active-high clock gating signal shown in Fig21. The output clock ‘CLKB’ timing
diagram and gated signal is shown in Fig22. If the gated signal goes low just after the positive clock edge
then a glitch is generated which can trigger the flip-flop when not desired.
A clock gating check is required when a gating signal controls the clock signal path in a logic circuit.
Consider the simplified gated clock circuit diagram shown in Fig21. The AND gate has two inputs which
includes clock signal and ‘enable’ signal also called gated signal. The AND gate output is called ‘gated
clock’.
Fig21. Clock Gating Circuit
Prior to clock gating check, few conditions must be considered. The gated clock is used to drive flip-flops
and helps to generate new clock. The generated clock means the clock which has different parameters
like phase difference, frequency change as compared to original clock (system clock). Another condition
is for gated signal. The gated signal should not be used as a clock to drive any flip-flops in the circuit. The
gated and clock signal can be connected to AND gate, OR gate or any logic that exhibits ‘AND’ function
or ‘OR’ function. It means clock gating signal is divided into two types.
Active-high clock gating signal and Active-low clock gating signal
Active-high clock gating signal occurs when logic circuit has ‘AND’ or ‘NAND’ function. The clock is
allowed to propagate through gated logic when the gated signal is active high otherwise the clock is
ceased to propagate when gated signal is active low. Similarly, the active-low clock gating signal occurs
when logic circuit has ‘OR’ or ‘NOR’ function. Here, when the gated signal is active low, then only clock
can propagate through the logic circuit.
Consider for example, the active-high clock gating signal shown in Fig21. The output clock ‘CLKB’ timing
diagram and gated signal is shown in Fig22. If the gated signal goes low just after the positive clock edge
then a glitch is generated which can trigger the flip-flop when not desired.
Fig22. Gated Signal causing Glitch in CLKB
Therefore, the glitch produced in ‘CLKB’ triggers the capture flip-flop which captures undesired output
causing whole system to produce incorrect results. Therefore, it is essential to perform clock gating
timing check to avoid circuit functionality failure in the system.
Setup Check for clock gating signal
The setup check says the signal should arrive before the active clock edge. In gated check, the enable
should arrive at the negative clock level otherwise it causes the system to produce incorrect results. The
Fig23 shows the enable signal is arriving before positive edge. Therefore, the output clock ‘CLKB’ is
produced without any glitches.
Therefore, the glitch produced in ‘CLKB’ triggers the capture flip-flop which captures undesired output
causing whole system to produce incorrect results. Therefore, it is essential to perform clock gating
timing check to avoid circuit functionality failure in the system.
Setup Check for clock gating signal
The setup check says the signal should arrive before the active clock edge. In gated check, the enable
should arrive at the negative clock level otherwise it causes the system to produce incorrect results. The
Fig23 shows the enable signal is arriving before positive edge. Therefore, the output clock ‘CLKB’ is
produced without any glitches.
Fig23. Clock Output without any glitches.
Similarly, for negative clock edge, the enable signal should arrive at negative clock level. If the enable
signal goes low at positive clock level then output contains glitches. Here, the negative edge arrives early
than desired. The Fig20 shows the glitchy output obtained when negative edge trigger is applied to flip-
flop.
Similarly, for negative clock edge, the enable signal should arrive at negative clock level. If the enable
signal goes low at positive clock level then output contains glitches. Here, the negative edge arrives early
than desired. The Fig20 shows the glitchy output obtained when negative edge trigger is applied to flip-
flop.
Fig24. Glitchy Output for negative clock edge
Therefore, it proves for both positive clock edge and negative clock edge, the gated signal should arrive
at the negative clock level. This is about clock gating setup analysis but it is essential to perform hold
analysis to ensure the gated signal arrives at the correct instant.
Hold Check
The hold check says the data should arrive after some time after the active clock edge. In gated clock,
the gated signal should arrive after active edge otherwise the AND gate produces glitches which
produces undesirable output. Therefore, gated check is required to avoid such timing violation.
In positive edge triggered flip-flop, if the gated signal arrives prior the negative edge, than it results in
glitchy output (same as Fig18) causing undesirable behavioral. Therefore, the gated signal should arrive
after negative edge and before positive edge. This ensures that the AND gate output is glitch free. The
Fig19 exhibits that the enable signal should arrive after negative edge.
Similarly, at negative clock edge, the signal should arrive after negative clock edge otherwise it results in
glitches. The Fig20 depicts the glitch produced if the signal arrives after positive edge. Similarly, the
gated check can be performed for OR function present in the circuit. The next section deals with the
asynchronous signals like reset present in the circuit.
Therefore, it proves for both positive clock edge and negative clock edge, the gated signal should arrive
at the negative clock level. This is about clock gating setup analysis but it is essential to perform hold
analysis to ensure the gated signal arrives at the correct instant.
Hold Check
The hold check says the data should arrive after some time after the active clock edge. In gated clock,
the gated signal should arrive after active edge otherwise the AND gate produces glitches which
produces undesirable output. Therefore, gated check is required to avoid such timing violation.
In positive edge triggered flip-flop, if the gated signal arrives prior the negative edge, than it results in
glitchy output (same as Fig18) causing undesirable behavioral. Therefore, the gated signal should arrive
after negative edge and before positive edge. This ensures that the AND gate output is glitch free. The
Fig19 exhibits that the enable signal should arrive after negative edge.
Similarly, at negative clock edge, the signal should arrive after negative clock edge otherwise it results in
glitches. The Fig20 depicts the glitch produced if the signal arrives after positive edge. Similarly, the
gated check can be performed for OR function present in the circuit. The next section deals with the
asynchronous signals like reset present in the circuit.
Recovery and Removal Timing check
Fig25. Circuit with asynchronous reset
Consider the circuit diagram shown in Fig25 that shows the reset signal is asynchronous with respect to
clock. Asynchronous reset means whenever the reset signal is applied, the flip-flop resets even though
clock signal has not arrive. The asynchronous reset waveform is shown in Fig26.
Fig26. Asynchronous Reset
Fig25. Circuit with asynchronous reset
Consider the circuit diagram shown in Fig25 that shows the reset signal is asynchronous with respect to
clock. Asynchronous reset means whenever the reset signal is applied, the flip-flop resets even though
clock signal has not arrive. The asynchronous reset waveform is shown in Fig26.
Fig26. Asynchronous Reset
Now, if the reset signal arrives within the restricted window (shown in Fig6) then the flip-flop enters in
metastable state for unbounded time interval. Fig27 depicts the circuit entering into metastable state
when reset arrives within the restricted region. Therefore, the output produced is between logic 1 and
logic 0. Therefore, the asynchronous signals like reset, set, clear, preset and so on should not arrive
within the restricted region.
Fig27. Asynchronous Reset causing metastability
metastable state for unbounded time interval. Fig27 depicts the circuit entering into metastable state
when reset arrives within the restricted region. Therefore, the output produced is between logic 1 and
logic 0. Therefore, the asynchronous signals like reset, set, clear, preset and so on should not arrive
within the restricted region.
Fig27. Asynchronous Reset causing metastability
Removal Timing Check
A removal timing check ensures that there is sufficient time between an active edge and an
asynchronous signal. Consider the circuit shown in Fig25. The reset signal is asynchronous with respect
to clock which may cause timing violation. Therefore, the removal timing check ensures that a signal
should remain stable till removal time after the active clock edge (shown in Fig28). This helps to avoid
metastability. This check is similar to hold time check.
Fig28. Removal Time Check
A removal timing check ensures that there is sufficient time between an active edge and an
asynchronous signal. Consider the circuit shown in Fig25. The reset signal is asynchronous with respect
to clock which may cause timing violation. Therefore, the removal timing check ensures that a signal
should remain stable till removal time after the active clock edge (shown in Fig28). This helps to avoid
metastability. This check is similar to hold time check.
Fig28. Removal Time Check
Recovery Timing Check
The recovery timing check and removal timing check contradict each other. It ensures the asynchronous
signal arrives prior the active clock edge arrives. In other words, this check ensures that there is enough
time to recover so that the next edge becomes active. Here, recover means the circuit requires time to
respond to the active clock edge. Therefore, the reset signal should arrive sufficient time before the
edge arrives (shown in Fig29). This check is similar to setup analysis.
Fig29. Recovery Time Check
This is about recovery and removal timing check. The next section describes about another timing check
called as half cycle paths. The half cycle paths are rarely found in the logic design. One such example for
half cycle path is SDRAM controller where both the clock edges are used. This check is useful to avoid
half cycle timing violation.
The recovery timing check and removal timing check contradict each other. It ensures the asynchronous
signal arrives prior the active clock edge arrives. In other words, this check ensures that there is enough
time to recover so that the next edge becomes active. Here, recover means the circuit requires time to
respond to the active clock edge. Therefore, the reset signal should arrive sufficient time before the
edge arrives (shown in Fig29). This check is similar to setup analysis.
Fig29. Recovery Time Check
This is about recovery and removal timing check. The next section describes about another timing check
called as half cycle paths. The half cycle paths are rarely found in the logic design. One such example for
half cycle path is SDRAM controller where both the clock edges are used. This check is useful to avoid
half cycle timing violation.
Half Cycle Check
The half cycle path is generally found when both the clock edges are used in the design. This path may
exist from a rising edge to a falling edge or vice versa. Fig30 shows the half cycle path where falling edge
is launching the data and rising edge is triggering the capture flip-flop. Since single cycle is used for both
launching and capturing the data therefore the setup timing check is with respect to rising edge whereas
hold time check is with respect to falling edge (Fig31).
Fig30. Circuit working on both clock edges (Negative edge and Positive edge)
Fig31. Half Cycle Path Timing Check
As shown in Fig31 the data should remain stable at least for flip-flop hold time. Also, the data should
become stable before the capture edge arrives. Therefore, the design consumes half cycle that helps in
increasing the clock frequency.
The paper deals with different timing checks and therefore the next section describe about the latches
used in the design. In this check the latch timing analysis is performed to ensure it does not produce any
glitch. This check explains that latches can be used in the design to improve performance.
The half cycle path is generally found when both the clock edges are used in the design. This path may
exist from a rising edge to a falling edge or vice versa. Fig30 shows the half cycle path where falling edge
is launching the data and rising edge is triggering the capture flip-flop. Since single cycle is used for both
launching and capturing the data therefore the setup timing check is with respect to rising edge whereas
hold time check is with respect to falling edge (Fig31).
Fig30. Circuit working on both clock edges (Negative edge and Positive edge)
Fig31. Half Cycle Path Timing Check
As shown in Fig31 the data should remain stable at least for flip-flop hold time. Also, the data should
become stable before the capture edge arrives. Therefore, the design consumes half cycle that helps in
increasing the clock frequency.
The paper deals with different timing checks and therefore the next section describe about the latches
used in the design. In this check the latch timing analysis is performed to ensure it does not produce any
glitch. This check explains that latches can be used in the design to improve performance.
Latch in Timing Analysis
Generally, it is advised that latches should be avoided in the design because they are not synthesizable.
But sometimes latches are useful because they help in increasing the clock frequency. This section
explains how latches help in improving the circuit performance.
Fig32. No Time Borrowing
Consider a circuit shown in Fig32. It has huge logic delay in between two flip-flops. This logic delay is
responsible for degrading the circuit performance. In Fig32, the 12ns logic delay reduces the circuit
frequency. Therefore, in order to increase the frequency the latch is placed in between two flip-flops
(Fig33). The latch works at positive clock level. The launch flip-flop launches input at positive clock edge.
At this edge, the latch is closed (Fig34) and therefore, any change at latch input will not affect the latch
output. Therefore, the capture flip-flop can capture the data safely.
Fig33. Use of latch to reduce logic delay
Generally, it is advised that latches should be avoided in the design because they are not synthesizable.
But sometimes latches are useful because they help in increasing the clock frequency. This section
explains how latches help in improving the circuit performance.
Fig32. No Time Borrowing
Consider a circuit shown in Fig32. It has huge logic delay in between two flip-flops. This logic delay is
responsible for degrading the circuit performance. In Fig32, the 12ns logic delay reduces the circuit
frequency. Therefore, in order to increase the frequency the latch is placed in between two flip-flops
(Fig33). The latch works at positive clock level. The launch flip-flop launches input at positive clock edge.
At this edge, the latch is closed (Fig34) and therefore, any change at latch input will not affect the latch
output. Therefore, the capture flip-flop can capture the data safely.
Fig33. Use of latch to reduce logic delay
Fig34. Working of Circuit in Fig33
At the negative clock edge, the launch flip-flop stops accepting the input. At this edge, the latch
launches the new output generated after 7ns delay and becomes stable before the next positive edge
arrives. Here, the data consumed 7ns plus the latch delay to reach at point ‘c’. It took about 5ns plus the
slave delay to arrive at the capture flip-flop output. Therefore, the launch flip-flop borrowed time from
latch to reduce the logic delay.
At the negative clock edge, the launch flip-flop stops accepting the input. At this edge, the latch
launches the new output generated after 7ns delay and becomes stable before the next positive edge
arrives. Here, the data consumed 7ns plus the latch delay to reach at point ‘c’. It took about 5ns plus the
slave delay to arrive at the capture flip-flop output. Therefore, the launch flip-flop borrowed time from
latch to reduce the logic delay.
Along with the different types discussed, many other types exist such as multicycle paths, multiple
clocks, false path timing check in the circuit and many more. In multicycle path, the reg-to-reg path
consumes more than one cycle to capture the data. In multiple clock timing check, two different clocks
are required to drive flip-flops in reg-to reg path. In this type, one clock drives launch flip-flop and
second clock drives capture flip-flop. In this paper, timing analysis with single clock is explained. The
next section is about different conditions that affects logic delay in the circuit.
Process-Voltage-Temperature (PVT) Variations
The timing analysis types assumed the logic gates introduces logic delay in the circuit. Therefore, more
logic gates in the path increase the delay whereas fewer gates in the path reduce the delay. In real life,
the chips are affected with process, voltage and temperature variation that affect the delay in the
circuit. For example, the circuit with hundred gates may possess less delay than the circuit with fewer
gates. Therefore, this section deals with the PVT variations that affect the circuit performance.
Process
The process indicates the technology or the channel length like 90nm, 45nm, 22nm and so on. These
values represent the length between MOSFET source and drain. These processes play a significant role in
affecting the delay in the circuit. Consider the circuit shown in Fig35.
Fig35. Process vs. Delay
clocks, false path timing check in the circuit and many more. In multicycle path, the reg-to-reg path
consumes more than one cycle to capture the data. In multiple clock timing check, two different clocks
are required to drive flip-flops in reg-to reg path. In this type, one clock drives launch flip-flop and
second clock drives capture flip-flop. In this paper, timing analysis with single clock is explained. The
next section is about different conditions that affects logic delay in the circuit.
Process-Voltage-Temperature (PVT) Variations
The timing analysis types assumed the logic gates introduces logic delay in the circuit. Therefore, more
logic gates in the path increase the delay whereas fewer gates in the path reduce the delay. In real life,
the chips are affected with process, voltage and temperature variation that affect the delay in the
circuit. For example, the circuit with hundred gates may possess less delay than the circuit with fewer
gates. Therefore, this section deals with the PVT variations that affect the circuit performance.
Process
The process indicates the technology or the channel length like 90nm, 45nm, 22nm and so on. These
values represent the length between MOSFET source and drain. These processes play a significant role in
affecting the delay in the circuit. Consider the circuit shown in Fig35.
Fig35. Process vs. Delay
In Fig35, the supply voltage and the output capacitance are kept constant whereas the channel length
varies. The channel possesses some resistance which limits current flow through the transistor. As a
result, the output capacitor consumes time to produce the output. As the channel length increases the
channel resistance also increases (Fig36). For example, the 90nm process possesses more resistance as
compared to 45nm. Therefore, the 90nm process consumes more time to produce output with respect
to 45nm keeping the output capacitor constant. Therefore, the large nodes increase the delay.
Therefore, it is vital to use the technology as small as possible.
Fig36. Resistance vs. Length
varies. The channel possesses some resistance which limits current flow through the transistor. As a
result, the output capacitor consumes time to produce the output. As the channel length increases the
channel resistance also increases (Fig36). For example, the 90nm process possesses more resistance as
compared to 45nm. Therefore, the 90nm process consumes more time to produce output with respect
to 45nm keeping the output capacitor constant. Therefore, the large nodes increase the delay.
Therefore, it is vital to use the technology as small as possible.
Fig36. Resistance vs. Length
Voltage
Consider the circuit (Fig37) where channel length is constant but the supply voltage (Vdd) varies. The
higher voltage source can supply large current whereas the low supply voltage can supply less current.
Therefore, the large supply voltage can charge capacitor at faster rate as compared to low supply
voltage. Consequently, the former supply consumes less time to produce the output in comparison with
low supply voltage. Therefore, the delay reduces with increase in power supply.
Fig37. Voltage supply vs. Delay
Consider the circuit (Fig37) where channel length is constant but the supply voltage (Vdd) varies. The
higher voltage source can supply large current whereas the low supply voltage can supply less current.
Therefore, the large supply voltage can charge capacitor at faster rate as compared to low supply
voltage. Consequently, the former supply consumes less time to produce the output in comparison with
low supply voltage. Therefore, the delay reduces with increase in power supply.
Fig37. Voltage supply vs. Delay
Temperature
Along with voltage and process variations, temperature variations greatly affect circuit delay. Consider a
metal wire under high temperature. As temperature increases, the atoms vibrate vigorously. Therefore,
the electrons collision rate with the vibrating atoms increases which results in less electrons propagating
through the metal wire. Since electrons are responsible for current flowing in the device, current
decreases with increase in temperature.
A similar phenomenon is observed in transistors. The channel is similar to metal wire whose current flow
decreases with increase in temperature. Due to decrease in current flow, more time is required to
charge the capacitor thereby increasing the circuit delay. Therefore, at higher temperatures the circuit
delay is high and at lower temperatures the circuit delay is small.
This discussion proves the Process-Voltage-Temperature variations are responsible for increasing or
decreasing the circuit delay. The STA engineers have to perform timing analysis repeatedly in order to
ensure the circuit performance is maintained. It is essential to make the chip work in extreme
temperatures like -40 to +150 degrees as well as with different voltage ranges from 0.9 V to 1.1 V. From
above discussion, it is proved that the best condition for minimum delay is maximum voltage, minimum
temperature and best technology whereas the worst condition is minimum voltage, maximum
temperature and worst technology.
The above discussion provides information regarding delay due to process, voltage and temperature
variations. The timing analysis is performed to ensure the circuit works properly even if these variations
occur. This analysis is performed at various stages in VLSI design flow. For example, it is performed
during synthesis to check whether the circuit meets the setup and hold condition. Similarly, in physical
design stage, interconnect or wire (used to connect different logic gates) introduces delay which affects
the circuit performance. Therefore, it is essential to check setup and hold violation.
Even if timing violation occurs, it is important to identify at early stage in the design cycle. It is not
impossible to avoid timing violation completely but few ways can be implemented to reduce them. The
following section provides ways to improve timing for any given circuit.
Along with voltage and process variations, temperature variations greatly affect circuit delay. Consider a
metal wire under high temperature. As temperature increases, the atoms vibrate vigorously. Therefore,
the electrons collision rate with the vibrating atoms increases which results in less electrons propagating
through the metal wire. Since electrons are responsible for current flowing in the device, current
decreases with increase in temperature.
A similar phenomenon is observed in transistors. The channel is similar to metal wire whose current flow
decreases with increase in temperature. Due to decrease in current flow, more time is required to
charge the capacitor thereby increasing the circuit delay. Therefore, at higher temperatures the circuit
delay is high and at lower temperatures the circuit delay is small.
This discussion proves the Process-Voltage-Temperature variations are responsible for increasing or
decreasing the circuit delay. The STA engineers have to perform timing analysis repeatedly in order to
ensure the circuit performance is maintained. It is essential to make the chip work in extreme
temperatures like -40 to +150 degrees as well as with different voltage ranges from 0.9 V to 1.1 V. From
above discussion, it is proved that the best condition for minimum delay is maximum voltage, minimum
temperature and best technology whereas the worst condition is minimum voltage, maximum
temperature and worst technology.
The above discussion provides information regarding delay due to process, voltage and temperature
variations. The timing analysis is performed to ensure the circuit works properly even if these variations
occur. This analysis is performed at various stages in VLSI design flow. For example, it is performed
during synthesis to check whether the circuit meets the setup and hold condition. Similarly, in physical
design stage, interconnect or wire (used to connect different logic gates) introduces delay which affects
the circuit performance. Therefore, it is essential to check setup and hold violation.
Even if timing violation occurs, it is important to identify at early stage in the design cycle. It is not
impossible to avoid timing violation completely but few ways can be implemented to reduce them. The
following section provides ways to improve timing for any given circuit.
Solutions
Pipeline
The huge logic delay between two flip-flops reduces the clock frequency. Therefore, the delay is
distributed in many stages to improve the circuit performance. The phenomenon in which the flip-flops
inserted in between the logic to optimize the long path in the circuit is called pipelining.
Fig38. Circuit without pipelining
Fig39. Pipelined Circuit
Pipeline
The huge logic delay between two flip-flops reduces the clock frequency. Therefore, the delay is
distributed in many stages to improve the circuit performance. The phenomenon in which the flip-flops
inserted in between the logic to optimize the long path in the circuit is called pipelining.
Fig38. Circuit without pipelining
Fig39. Pipelined Circuit
Synchronization
In Fig38, between the input ‘c’ and the multiplier three flip-flops are inserted to match the timing. For
example, consider the inputs given in Fig33 are a = 2, b=5 and c=5. The capture flip-flop produces ‘75’ as
output. Here, the inputs applied to multiplier and adder blocks should reach at correct instant otherwise
the circuit will produce incorrect results.
Therefore, after pipelining as well, the inputs should reach at correct instant to produce correct output.
In Fig39, after each logic block a flip-flop is inserted to reduce the critical path between two flip-flops. As
a result, the inputs ‘a’, ‘b’ and ‘c’ are not synchronous with each other resulting in wrong output.
Therefore, the input ‘c’ is flopped thrice to make all inputs synchronous with each other. This aid in
improving the critical path as well as the synchronization problem is avoided.
Complex Cells
Fig40. Complex cells
Rather than using circuit with more logic levels (Fig40), use a complex gates to reduce the interconnect
delay between the logic gates. Therefore, the load capacitance after every logic cell is reduced thereby
decreasing the delay between input and output. Therefore, the synthesizer uses complex cells to reduce
delay in the design.
Many such ways are used to fix timing violation such as reduce clock frequency, insert high speed cells,
Interfaces and many more. The important observation is that the setup and hold condition are
contradictory to each other. Therefore, it is always tradeoff between these two checks as the conditions
contradict each other. Therefore, it is crucial to check for both checks after solving one issue.
In Fig38, between the input ‘c’ and the multiplier three flip-flops are inserted to match the timing. For
example, consider the inputs given in Fig33 are a = 2, b=5 and c=5. The capture flip-flop produces ‘75’ as
output. Here, the inputs applied to multiplier and adder blocks should reach at correct instant otherwise
the circuit will produce incorrect results.
Therefore, after pipelining as well, the inputs should reach at correct instant to produce correct output.
In Fig39, after each logic block a flip-flop is inserted to reduce the critical path between two flip-flops. As
a result, the inputs ‘a’, ‘b’ and ‘c’ are not synchronous with each other resulting in wrong output.
Therefore, the input ‘c’ is flopped thrice to make all inputs synchronous with each other. This aid in
improving the critical path as well as the synchronization problem is avoided.
Complex Cells
Fig40. Complex cells
Rather than using circuit with more logic levels (Fig40), use a complex gates to reduce the interconnect
delay between the logic gates. Therefore, the load capacitance after every logic cell is reduced thereby
decreasing the delay between input and output. Therefore, the synthesizer uses complex cells to reduce
delay in the design.
Many such ways are used to fix timing violation such as reduce clock frequency, insert high speed cells,
Interfaces and many more. The important observation is that the setup and hold condition are
contradictory to each other. Therefore, it is always tradeoff between these two checks as the conditions
contradict each other. Therefore, it is crucial to check for both checks after solving one issue.
Conclusion
Therefore, concluding this, the timing analysis is an important analysis in VLSI design flow. The circuit
has the tendency to produce wrong results without this analysis. Therefore, this analysis is performed to
avoid undesirable output. This analysis is not limited to reg-to-reg path but it also includes input-to-
output, reg-to-output, half cycle path, clock gating path and so on. All these analysis are performed to
ensure the circuit works properly in all possible conditions.
References
1. http://www.vlsi-expert.com/p/static-timing-analysis.html
2. Bhasker J. and Chadha Rakesh, Static Timing Analysis – A practical book for nanometer design,
Springer Publications, 2009
Blog
To perform timing analysis in given circuit, it is important to understand the timing paths present in the circuit.
Timing Paths
The circuit diagram given above shows the timing paths in the sequential circuit.
Therefore, concluding this, the timing analysis is an important analysis in VLSI design flow. The circuit
has the tendency to produce wrong results without this analysis. Therefore, this analysis is performed to
avoid undesirable output. This analysis is not limited to reg-to-reg path but it also includes input-to-
output, reg-to-output, half cycle path, clock gating path and so on. All these analysis are performed to
ensure the circuit works properly in all possible conditions.
References
1. http://www.vlsi-expert.com/p/static-timing-analysis.html
2. Bhasker J. and Chadha Rakesh, Static Timing Analysis – A practical book for nanometer design,
Springer Publications, 2009
Blog
To perform timing analysis in given circuit, it is important to understand the timing paths present in the circuit.
Timing Paths
The circuit diagram given above shows the timing paths in the sequential circuit.
1. The combinational path between any two flip-flops is reg-to-reg path.
2. The path from chip input till the first flip-flop input is called input-to-reg path.
3. The path from flip-flop till the circuit output is called reg-to-output path.
4. The combinational part excluding the registers in the circuit is called input-to-output path.
Basic Terms -
1. Logic Delay - The combinational logic (NAND, XOR, NOR, etc. gates and MUX, DECODERS and so
on) introduces produces output after some amount of time.
2. Long Path - The maximum delay introduced by a path in the combinational logic is called Long Path
(Critical Path).
3. Short Path - The minimum delay introduced by a path in the combinational logic is called Short
Path.
2. The path from chip input till the first flip-flop input is called input-to-reg path.
3. The path from flip-flop till the circuit output is called reg-to-output path.
4. The combinational part excluding the registers in the circuit is called input-to-output path.
Basic Terms -
1. Logic Delay - The combinational logic (NAND, XOR, NOR, etc. gates and MUX, DECODERS and so
on) introduces produces output after some amount of time.
2. Long Path - The maximum delay introduced by a path in the combinational logic is called Long Path
(Critical Path).
3. Short Path - The minimum delay introduced by a path in the combinational logic is called Short
Path.
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