Traffic light Controller Design

Traffic light controller Design using mealy and moore model.

1. University of Mauritius
Faculty of Engineering
Department of Electrical and Electronic Engineering

Programme: BEng(Hons) Electrical and electronic Engineering
(Year 3)

Module: Electronic System Design
TRAFFIC LIGHT CONTROLLER DESIGN
IVAN TIM OLOYA:0900153
KAVI GOPAUL:0913166
WILLIAM ULRICH JOUBERT:0900145
Date Submitted : 03/07/2013

2. 1

1. Literature Review

1.1 State Machines
State machines, also known as finite state machines are circuits that can performs different sets
of sequences of operation controlled by a clock and other inputs.
The state machine can be divided into
(i) Completely specified FSM
(ii) Incompletely specified FSM

Unlike the other, the CS FSM is one which every internal states are defined for each and every
input possibilities.
The type of output of the CSFSM can be categorised as
(i) Mealy Model : where output is dependent upon the present states and the inputs.
(ii) Moore Model : where output is dependent upon present states only.
For designing states machines, once the type of CSFSM has been decided the state diagram showing the
sequence of operation can be obtained and its state table can be easily obtained. Furthermore the state
table can be minimized by using either row matching method or implication chart method. Once the
final state table is obtained designing the system can statrt.
1.2 Programmable Logic Devices (PLD)
A PLD contains a large number of logic gates within a single a package, but allows a user to determine
how they are interconnected; this technology is known as un-committed logic. Since the gate are not
committed to any specific function at the time of manufacture, the various gates within a device and the
interconnections are arranged within one or more arrays. For this reason this form of logic is also known
as array logic. There are many forms of array logic, some of the most widely used include;
a) PLA programmable logic array
b) PAL programmable array logic
c) GAL genetic array logic
d) PROM programmable read only memory
e) CPLD complex programmable logic device
f) FPGA field programmable gate array


1.3 Existing Model

1.3.1 Specification

In this model, a traffic light controller is needed to control the traffic between a main street
and a side street.

3. 2

The main street needs to have green light for 30s followed by 5s transitional caution light
and finally red light. The side street needs to have red light as long as there is green light or
yellow light on the main and green light when the main has a red.

Figure 1.1 Sequence of operation
The table below summarises the sequence and duration

Duration/s Main Side
30 Green (MG) Red (SR)
5 Yellow (MY) Red (SR)
30 Red (MR) Green (SG)
5 Red (MR) Yellow (SY)
Table 1.1 sequence and duration
The controller needs to have six defined outputs and a timer to control the duration of the
lights.

Figure 1.2 Block diagram of the traffic light controller

1.3.2 Steps used in designing the system

1. Timer, T
T has a frequency,f1 , and duty ratio,D, to control sequence duration of 30s followed by 5s.

4. 3

(i) Frequency ,f1
??????
1=
1
35

=0.0286 �??????
(ii) duty ratio, D
�=
30
35

=0.857

When T is high, this corresponds to duration of 30s and when T is low, the duration will be 5s.

Figure 1.3 Timer duration control
2. Finding state equations and output equations.
To find the state equations and output equations the state diagram is required. The controller has four
possibilities of output between the main and side street hence they are defined as states and are
assigned a variable as per the table below.

State Representation
S0 MG and SR
S1 MY and SR
S2 MR and SG
S3 MR and SY

Finally the state diagram is as follows.
Figure 1.4 State Diagram

5. 4

For simplicity only the high outputs of the respective states has been used .


3. State table
The state table is obtained from the state diagram and the states are assigned as per the table
below.

state Binary assignment
Q1 Q0
S0 0 0
S1 0 1
S2 1 0
S3 1 1

TRANSITION TABLE FOR MOORE MACHINE



2. System design

2.1 Moore Model

The new model will designed using the similar concept of the existing model and the
feature to be added is the pedestrian lights. The procedures to be followed are:
1. Find the possible outputs
2. Identify the sequence hence the state diagram
3. State table and excitation table
4. State equations and output equations
5. Logic design

PRESENT
STATES
INPUTS NEXT
STATES
OUTPUTS
Q1 Q0 T Q1+ Q0+ MR MY MG SR SY SG
0 0 0 0 1 0 0 1 1 0 0
0 0 1 0 0 0 0 1 1 0 0
0 1 0 0 1 0 1 0 1 0 0
0 1 1 1 0 0 1 0 1 0 0
1 0 0 1 1 1 0 0 0 0 1
1 0 1 1 0 1 0 0 0 0 1
1 1 0 1 1 1 0 0 0 1 0
1 1 1 0 0 1 0 0 0 1 0

6. 5

1. According to the specifications the possible outputs are summarised in the table
below

TRANSISTION
TIME(T)/SECONDS
MAIN ROAD (M) SIDE ROAD (S) PEDESTRIAN(P)
25 GREEN (G) RED(R) RED(R)
5 YELLOW (Y) RED(R) RED(R)
25 RED(R) GREEN (G) RED(R)
5 RED(R) YELLOW (Y) RED(R)
25 RED(R) RED(R) GREEN (G)
5 RED(R) RED(R) GREEN (G)
2.1 sequence of operation and duration of each states

2.1.2 State Diagram
Fig 2.2 state diagram of the controller

�0
MGSRPR

�1
MYSRPR

�2
MRSGPR

�5
MRSRPY

�3
MRSYPR

�4
MRSRPG

�=1/C=X

T=0/C=X

T=1/C=
X
T=0/C=
X
�=
0/C=X

7. 6


Hence the following state transition table and excitation table are obtained.

NEXT
STATES
OUTPUT
Z
T C
PRESENT
STATES
00 01 10 11
S0 S1 S1 S0 S1 MGSRPR
S1 S1 S1 S2 S2 MYSRPR
S2 S3 S3 S2 S2 MRSGPR
S3 S3 S3 S0 S4 MRSYPR
S4 S5 S5 S4 S4 MRSRPG
S5 S5 S5 S0 S0 MRSRPY
2.1 state transition table for the controller

8. 7






Table 2.2 Excitation table of the controller

From the excitation table the flip flop equations and the output equations can be obtained and
minimised using k-map.
PRESENT STATE INPUT NEXT STATE OUTPUT Flip Flop i/p
Q2 Q1 Q0 T C Q2
+
Q1
+
Q0
+
MR MY MG SR SY SG PR PY PG D2 D1 D0
0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0 1
0 0 0 0 1 0 0 1 0 0 1 1 0 0 1 0 0 0 0 1
0 0 0 1 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0
0 0 0 1 1 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0
0 0 1 0 0 0 0 1 0 1 0 1 0 0 1 0 0 0 0 1
0 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 0 0 0 1
0 0 1 1 0 0 1 0 0 1 0 1 0 0 1 0 0 0 1 0
0 0 1 1 1 0 1 0 0 1 0 1 0 0 1 0 0 0 1 0
0 1 0 0 0 0 1 1 1 0 0 0 0 1 1 0 0 0 1 1
0 1 0 0 1 0 1 1 1 0 0 0 0 1 1 0 0 0 1 1
0 1 0 1 0 0 1 0 1 0 0 0 0 1 1 0 0 0 1 0
0 1 0 1 1 0 1 0 1 0 0 0 0 1 1 0 0 0 1 0
0 1 1 0 0 0 1 1 1 0 0 0 1 0 1 0 0 0 1 1
0 1 1 0 1 0 1 1 1 0 0 0 1 0 1 0 0 0 1 1
0 1 1 1 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0
0 1 1 1 1 1 0 0 1 0 0 0 1 0 1 0 0 1 0 0
1 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 1 1 0 1
1 0 0 0 1 1 0 1 1 0 0 1 0 0 0 0 1 1 0 1
1 0 0 1 0 1 0 0 1 0 0 1 0 0 0 0 1 1 0 0
1 0 0 1 1 1 0 0 1 0 0 1 0 0 0 0 1 1 0 0
1 0 1 0 0 1 0 1 1 0 0 1 0 0 0 1 0 1 0 1
1 0 1 0 1 1 0 1 1 0 0 1 0 0 0 1 0 1 0 1
1 0 1 1 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0
1 0 1 1 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0
1 1 0 0 0 X X X X X X X X X X X X X X X
1 1 0 0 1 X X X X X X X X X X X X X X X
1 1 0 1 0 X X X X X X X X X X X X X X X
1 1 0 1 1 X X X X X X X X X X X X X X X
1 1 1 0 0 X X X X X X X X X X X X X X X
1 1 1 0 1 X X X X X X X X X X X X X X X
1 1 1 1 0 X X X X X X X X X X X X X X X
1 1 1 1 1 X X X X X X X X X X X X X X X

9. 8


1.4 Flip flop input equation and Output equation

�
2=�
2�+�
2�
0+�
1�
0��

�
2=�
2(�+�
0)+�
1�
0��

�
1=�
1�+�
1�
0+�
2 �
1�
0�

10. 9


�
0=�

Output Equations


??????�=�2+�1



????????????=�2 �1�0




??????�=�2 �1 �0




00 01 11 10
0 0 1 1
1 1 1 X X
00 01 11 10
0 0 1 0 0
1 0 0 X X
00 01 11 10
0 1 0 0 0
1 0 0 X X
Q1Q0
Q2
Q1Q0
Q2
Q1Q0
Q2
Q1Q0
Q2

11. 10

��=�1




�??????=�1�0



��=�1�0



��=�2



��=�2�0




�??????=�2�0




00 01 11 10
0 1 1 0 0
1 1 1 X X
00 01 11 10
0 0 0 1 0
1 0 0 X X
00 01 11 10
0 0 0 0 1
1 0 0 X X
00 01 11 10
0 1 1 1 1
1 0 0 X X
00 01 11 10
0 0 0 0 0
1 1 0 X X
00 01 11 10
0 0 0 0 0
1 0 1 X X
Q1Q0
Q2
Q1Q0
Q2
Q1Q0
Q2
Q1Q0
Q2
Q1Q0
Q2

12. 11

2.2 Mealy Model
2.2.1 STATE DIAGRAM
















2.2.2 STATE TABLE
TABLE 1.
BINARY ASSIGMENT
STATES
S0 000
S1 001
S2 010
S3 011
S4 100
S5 101
Table 2.3 Binary assignment

SO
S1
S2
S5
S3
S4

T/P=X/
MGSRPR

� /P=X/
MYSRPR
T/P=X
/
� /P=X/
MRSYPR
� /P=X/
MRSRPY

13. 12

Q1Q0
TP
Q2=0
Q1Q0
TP Q2=1
Q1Q0
TP
Q2=0
Q1Q0
TP Q2=1

2.4 excitation table of mealy model
2.2.3 State Equation


00 01 11 10 00 01 11 10
00 0 0 0 0 00 1 1 1 1
01 0 0 0 0 01 1 1 0 0
11 0 0 1 0 11 0 0 0 0
10 0 0 0 0 10 0 0 0 0

�2=�2�1�0+�2�1�+�2 �1�0��

00 01 11 10 00 01 11 10
00 0 0 0 0 00 0 0 0 0
01 0 0 1 1 01 0 0 0 0
11 1 1 0 0 11 0 0 0 0
10 1 1 1 1 10 0 0 0 0

�1=�2 �1�0+�2 �1� +�2�1 �0�



PRESENT STATE INPUT NEXT STATE OUTPUT
Q2 Q1 Q0 T P Q2
+
Q1
+
Q0
+
MG MY MR SG SY SR PG PY PR
0 0 0 0 X 0 0 1 1 0 0 0 0 0 0 0 1
0 0 0 1 X 0 0 0 1 0 0 0 0 0 0 0 1
0 0 1 0 X 0 0 1 0 1 0 0 0 0 0 0 1
0 0 1 1 X 0 1 0 0 1 0 0 0 0 0 0 1
0 1 0 0 X 0 1 1 0 0 1 1 0 0 0 0 1
0 1 0 1 X 0 1 0 0 0 1 1 0 0 0 0 1
0 1 1 0 X 0 1 1 0 0 1 0 1 0 0 0 1
0 1 1 1 0 0 0 0 0 0 1 0 1 0 0 0 1
0 1 1 1 1 1 0 0 0 0 1 0 1 0 0 0 1
1 0 0 0 X 1 0 1 0 0 1 0 0 1 1 0 0
1 0 0 1 X 1 0 0 0 0 1 0 0 1 1 0 0
1 0 1 0 X 1 0 1 0 0 1 0 0 1 0 1 0
1 0 1 1 X 0 0 0 0 0 1 0 0 1 0 1 0

14. 13

Q1Q0
TP
Q2=0
Q1Q0
TP Q2=1
Q1Q0
TP
Q2=0
Q1Q0
TP Q2=1
Q1Q0
TP
Q2=0
Q1Q0
TP Q2=1
Q1Q0
TP
Q2=0
Q1Q0
TP Q2=1




�0=�2�+�1 �



00 01 11 10 00 01 11 10
00 1 1 1 1 00 0 0 0 0
01 0 0 0 0 01 0 0 0 0
11 0 0 0 0 11 0 0 0 0
10 0 0 0 0 10 0 0 0 0

??????�=�2�1�0


00 01 11 10 00 01 11 10
00 0 0 0 0 00 0 0 0 0
01 1 1 1 1 01 0 0 0 0
11 0 0 0 0 11 0 0 0 0
10 0 0 0 0 10 0 0 0 0

????????????=�2�1 �0


00 01 11 10 00 01 11 10
00 0 0 0 0 00 1 1 1 1
01 0 0 0 0 01 1 1 1 1
11 1 1 1 1 11 0 0 0 0
10 1 1 1 1 10 0 0 0 0
00 01 11 10 00 01 11 10
00 1 1 0 0 00 1 1 0 0
01 1 1 0 0 01 1 1 0 0
11 1 1 0 0 11 0 0 0 0
10 1 1 0 0 10 0 0 0 0

15. 14

Q1Q0
TP
Q2=1
Q1Q0
TP Q2=1
Q1Q0
TP
Q2=0
Q1Q0
TP Q2=1
Q1Q0
TP
Q2=0
Q1Q0
TP Q2=1
Q1Q0
TP
Q2=0
Q1Q0
TP Q2=1

??????�= �2 �1+�2�1


00 01 11 10 00 01 11 10
00 00 0 0 0 0
01 01 0 0 0 0
11 11 0 0 0 0
10 1 1 1 1 10 0 0 0 0

SG=�2 �1�0

00 01 11 10 00 01 11 10
00 0 0 0 0 00 0 0 0 0
01 0 0 0 0 01 0 0 0 0
11 1 1 1 1 11 0 0 0 0
10 0 0 0 0 10 0 0 0 0

SY=�2 �1�0



00 01 11 10 00 01 11 10
00 1 1 1 1 00 1 1 1 1
01 1 1 1 1 01 1 1 1 1
11 0 0 0 0 11 0 0 0 0
10 0 0 0 0 10 0 0 0 0

��=�1

00 01 11 10 00 01 11 10
00 1 1 1 1 00 0 0 0 0
01 0 0 0 0 01 1 1 1 1
11 0 0 0 0 11 0 0 0 0
10 0 0 0 0 10 0 0 0 0

��=�2�1�0 �??????=�2�1 �0

16. 15

Q1Q0
TP
Q2=0
Q1Q0
TP Q2=1




00 01 11 10 00 01 11 10
00 1 1 1 1 00 0 0 0 0
01 1 1 1 1 01 0 0 0 0
11 1 1 1 1 11 0 0 0 0
10 1 1 1 1 10 0 0 0 0

��=�2

17. 16

18. 17


3. Implementation using FPLA

A programmable logic array is a kind of programmable logic device used to implement combinational
circuits. The structure of the PLA is shown in (design of FPLA). This show an arrangement with five inputs
(Q2, Q1, Q0, T, P) which are inverted to produce 5 pairs of complementary inputs. The signals are then
each connected through an array of fusible links. These fuses are initially all intact, but they may be
blown selectively to determine the pattern of connections between the inputs. Signals and the AND
gates. In this way each AND gate corresponds to an individual minterm. A second array of fuses is used
to connect the outputs of the AND gates to a collection of OR gates. These OR gates combine the
relevant minterms to produce various outputs.
In order to represent symbolically the large number of gates and interconnections within a typical
device, it is conventional to adopt a more compact notation that reduces a large number of
interconnecting wires within various array.
The symbols used when drawing logic arrays are shown in (design of FPLA). Here a single line is drawn to
represent all inputs to the gate and a cross used to indicate those inputs lines that are connected to that
gate.

19. 18

The product terms were obtained from the moore model design in section 2

Table 3.1 personality matrix of FPLA

INPUTS OUTPUTS
Product
term
Q2 Q1 Q0 T P D2 D1 D0 MG MY MR SG SY SR PG PY PR
�2�1�0 1 0 0 - - 1 - - - - - - - - - - -
�2�1� 1 1 - 0 - 1 - - - - - - - - - - -
�2�0�� 1 1 1 1 1 1 - - - - - - - - - - -
�2�1�0 0 1 0 - - - 1 - - - - - - - - - -
�2�1� 0 1 - 0 - - 1 - - - - - - - - - -
�2�1�0� 0 0 1 1 - - 1 - - - - - - - - - -
�2� 0 - - 0 - - - 1 - - - - - - - - -
�1� - 0 - 0 - - - 1 - - - - - - - - -
�2�1�0 0 0 0 - - - - - 1 - - - - - - - -
�2�1�0 0 0 1 - - - - - - 1 - - - - - - -
�2�1 0 1 - - - - - - - - 1 - - - - - -
�2�1 1 0 - - - - - - - - 1 - - - - - -
�2�1�0 0 1 0 - - - - - - - - 1 - - - - -
�2�1�0 0 1 1 - - - - - - - - - 1 - - - -
�1 - 0 - - - - - - - - - - - 1 - - -
�2�1�0 1 0 0 - - - - - - - - - - - 1 - -
�2�1�0 1 0 1 - - - - - - - - - - - - 1 -
�2 0 - - - - - - - - - - - - - - - 1

20. 19


Figure 3.2 Design of FPLA
4. Implementation on the GAL

The system to be implemented on the GAL is a sequential circuit. The sequence of
operation from the state table and the output equations obtained from the moore

21. 20

model will be used to program the GAL in wincupl. Since there are 9 outputs 2
G16V8 ICs is used to implement the system.
1.4.1 design file for first IC
On the first IC the flip flop states will be generated and it will also contain the
output for the main red.
(a) Program file

Name ESD ASS ;
PartNo 00 ;
Date 26-Feb-13 ;
Revision 01 ;
Designer Engineer ;
Company UOM ;
Assembly None ;
Location REDUIT ;
Device g16v8 ;

/* *************** INPUT PINS *********************/
PIN 1 = CLK ; /* clock */
PIN 2 = T ; /* duration control
*/
PIN 3 = C ; /* debounce switch
*/

/* *************** OUTPUT PINS *********************/
PIN 12 = Q0 ; /* state outputs
*/
PIN 13 = Q1 ; /* */
PIN 14 = Q2 ; /* */
PIN 15 = MR;

FIELD state = [Q0..2];
$REPEAT i=[0..5] /*******define the states**********/
$DEFINE S{i} 'b'{i}
$REPEND
FIELD MODE=[T,C]; /*********group inputs******/
GO = MODE : 0;
FOLLOW = MODE : 1;
NOPED = MODE : 2;
PED = MODE : 3;

SEQUENCE state { /*********sequence of operations*****/
PRESENT S0
IF GO NEXT S1;
IF FOLLOW NEXT S1;
DEFAULT NEXT S0;

PRESENT S1
IF GO NEXT S1;
IF FOLLOW NEXT S1;
DEFAULT NEXT S2;

PRESENT S2
IF GO NEXT S3;
IF FOLLOW NEXT S3;
DEFAULT NEXT S2;

PRESENT S3

22. 21

IF GO NEXT S3;
IF FOLLOW NEXT S3;
IF NOPED NEXT S0;
IF PED NEXT S4;

PRESENT S4
IF GO NEXT S5;
IF FOLLOW NEXT S5;
DEFAULT NEXT S4;

PRESENT S5
IF GO NEXT S5;
IF FOLLOW NEXT S5;
DEFAULT NEXT S0;
}
MR = Q2#Q1; /* main red output */

1.2 Jedec File for first IC

CUPL(WM) 5.0a Serial# 60008009
Device g16v8ms Library DLIB -h-40-11
Created Mon Mar 04 18:18:26 2013
Name ESD ASS
Partno 00
Revision 01
Date 26-Feb-13
Designer Engineer
Company UOM
Assembly None
Location REDUIT
*QP20
*QF2194
*QV31
*G0
*F0
*L01024 11111111111111111111111111111111
*L01056 11111111111111111111110111111111
*L01088 11111111111111111111111111011111
*L01280 10111111111111111111110111101101
*L01312 01110111111111111111111011011101
*L01344 11111111111111111111110111101110
*L01536 10111111111111111111111011011101
*L01568 01111111111111111111111011101101
*L01600 11111111111111111111111011011110
*L01792 10111111111111111111111011011111
*L01824 10111111111111111111111111101111
*L02048 000011110011000000110 00000100000
*L02112 00000000111110001111111111111111
*L02144 11111111111111111111111111111111
*L02176 111111111111111101
*C2F6B
*P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
*V0001 C11XXXXXXNXLLLLXXXXN
*V0002 C11XXXXXXNXLLLLXXXXN
*V0003 C01XXXXXXNXHLLLXXXXN
*V0004 C01XXXXXXNXHLLLXXXXN
*V0005 C11XXXXXXNXLHLHXXXXN
*V0006 C11XXXXXXNXLHLHXXXXN
*V0007 C01XXXXXXNXHHLHXXXXN
*V0008 C01XXXXXXNXHHLHXXXXN
*V0009 C11XXXXXXNXLLHHXXXXN

23. 22

*V0010 C11XXXXXXNXLLHHXXXXN
*V0011 C01XXXXXXNXHLHHXXXXN
*V0012 C01XXXXXXNXHLHHXXXXN
*V0013 C11XXXXXXNXLLLLXXXXN
*V0014 C11XXXXXXNXLLLLXXXXN
*V0015 C01XXXXXXNXHLLLXXXXN
*V0016 C01XXXXXXNXHLLLXXXXN
*V0017 C11XXXXXXNXLHLHXXXXN
*V0018 C11XXXXXXNXLHLHXXXXN
*V0019 C01XXXXXXNXHHLHXXXXN
*V0020 C01XXXXXXNXHHLHXXXXN
*V0021 C10XXXXXXNXLLLLXXXXN
*V0022 C10XXXXXXNXLLLLXXXXN
*V0023 C00XXXXXXNXHLLLXXXXN
*V0024 C00XXXXXXNXHLLLXXXXN
*V0025 C10XXXXXXNXLHLHXXXXN
*V0026 C10XXXXXXNXLHLHXXXXN
*V0027 C00XXXXXXNXHHLHXXXXN
*V0028 C00XXXXXXNXHHLHXXXXN
*V0029 C10XXXXXXNXLLLLXXXXN
*V0030 C10XXXXXXNXLLLLXXXXN
*V0031 C00XXXXXXNXHLLLXXXXN
* BC23

1.3 Fuse Plot


**************************************************************************
*****
ESD
**************************************************************** **********
*****

CUPL(WM) 5.0a Serial# 60008009
Device g16v8ms Library DLIB -h-40-11
Created Wed Feb 27 21:29:45 2013
Name ESD ASS
Partno 00
Revision 01
Date 26-Feb-13
Designer Engineer
Company UOM
Assembly None
Location REDUIT

==========================================================================
=====
Expanded Product Terms
=============================== ===========================================
=====

FOLLOW =>
C & !T

GO =>
!C & !T

24. 23

MODE =>
T , C

MR =>
Q2
# Q1

NOPED =>
!C & T

PED =>
C & T

Q0.d =>
Q1 & !Q2 & !T
# !Q1 & !T

Q1.d =>
Q0 & Q1 & !Q2 & !T
# Q0 & !Q1 & !Q2 & T
# !Q0 & Q1 & !Q2

Q2.d =>
Q0 & !Q1 & Q2 & !T
# C & Q0 & Q1 & !Q2 & T
# !Q0 & !Q1 & Q2

state =>
Q0 , Q1 , Q2

MR.oe =>
1

25. 24

==========================================================================
=====
Symbol Table
==========================================================================
=====

Pin Variable Pterms Max Min
Pol Name Ext Pin Type Used Pterms Level
--- -------- --- --- ---- ------ ------ -----

C 3 V - - -
CLK 1 V - - -
FOLLOW 0 I 1 - -
GO 0 I 1 - -
MODE 0 F - - -
MR 15 V 2 7 1
NOPED 0 I 1 - -
PED 0 I 1 - -
Q0 12 V - - -
Q0 d 12 X 2 8 1
Q1 13 V - - -
Q1 d 13 X 3 8 1
Q2 14 V - - -
Q2 d 14 X 3 8 1
T 2 V - - -
state 0 F - - -
MR oe 15 D 1 1 0


LEGEND D : default variable F : field G : group
I : intermediate variable N : node M : extended node
U : undefined V : vari able X : extended
variable
T : function

26. 25

==========================================================================
=====
Fuse Plot
==========================================================================
=====

Syn 02192 x Ac0 02193 -

Pin #19 02048 Pol x 02120 Ac1 -
00000 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00032 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00064 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00096 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00128 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00160 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00192 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00224 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Pin #18 02049 Pol x 02121 Ac1 -
00256 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00288 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00320 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00352 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00384 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00416 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00448 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00480 xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
Pin #17 02050 Pol x 02122 Ac1 -
00512 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00544 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00576 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00608 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00640 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00672 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00704 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00736 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Pin #16 02051 Pol x 02123 Ac1 -
00768 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00800 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00832 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00864 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00896 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00928 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00960 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00992 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Pin #15 02052 Pol - 02124 Ac1 -
01024 --------------------------------
01056 ---------------------- x---------
01088 -------------------------- x-----
01120 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01152 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01184 xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
01216 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01248 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Pin #14 02053 Pol - 02125 Ac1 x
01280 -x--------------------x----x--x-
01312 x---x------------------x--x---x-
01344 ---------------------- x----x---x
01376 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01408 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx

27. 26

01440 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01472 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01504 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Pin #13 02054 Pol - 02126 Ac1 x
01536 -x---------------------x--x---x-
01568 x---------------------- x---x--x-
01600 ----------------------- x--x----x
01632 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01664 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01696 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01728 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01760 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Pin #12 02055 Pol - 02127 Ac1 x
01792 -x--------------------- x--x-----
01824 -x------------------------- x----
01856 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01888 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01920 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01952 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01984 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
02016 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx


LEGEND X : fuse not blown
- : fuse blown

28. 27

==========================================================================
=====
Chip Diagram
==========================================================================
=====

______________
| ESD |
CLK x---|1 20|---x Vcc
T x---|2 19|---x
C x---|3 18|---x
x---|4 17|---x
x---|5 16|---x
x---|6 15|---x MR
x---|7 14|---x Q2
x---|8 13|---x Q1
x---|9 12|---x Q0
GND x---|10 11|---x
|______________|



1.4 Design file for second IC
The second IC will contain the rest of the outputs that is the main yellow and
green,side red,yellow and green and the pedestrian also.
Name output ;
PartNo 00 ;
Date 03-Mar-13 ;
Revision 01 ;
Designer Engineer ;
Company Home ;
Assembly None ;
Location ;
Device g16v8 ;

/* *************** INPUT PINS *********************/
PIN 2 = Q0 ; /*
*/
PIN 3 = Q1 ; /* state
*/
PIN 4 = Q2 ; /* inputs
*/

/* *************** OUTPUT PINS *********************/
PIN [12..19] = [U0..7] ; /*
*/

U0 =!Q2&!Q1&Q0; /*main yellow*/
U1 = !Q2&!Q1&!Q0; /*main green*/
U2 = !Q1; /*side red*/
U3 = Q1&Q0; /*side yellow*/
U4 = Q1&!Q0; /*side green*/
U5 = !Q2; /*pedestrian red*/
U6 = Q2&Q0; /*pedestrian yellow*/

29. 28

U7 = !Q0&Q2; /*pedestrian green*/



1.5 Jedec file

CUPL(WM) 5.0a Serial# 60008009
Device g16v8s Library DLIB-h-40-9
Created Mon Mar 04 18:30:41 2013
Name output
Partno 00
Revision 01
Date 03-Mar-13
Designer Engineer
Company Home
Assembly None
Location
*QP20
*QF2194
*QV27
*G0
*F0
*L00000 10111111011111111111111111111111
*L00256 01111111011111111111111111111111
*L00512 11111111101111111111111111111111
*L00768 10110111111111111111111111111111
*L01024 01110111111111111111111111111111
*L01280 11111011111111111111111111111111

30. 29

*L01536 10111011101111111111111111111111
*L01792 01111011101111111111111111111111
*L02048 11111111001100000011000000100000
*L02112 00000000000000001111111111111111
*L02144 11111111111111111111111111111111
*L02176 111111111111111110
*C2863
*P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
*V0001 X000XXXXXNXLHHLLHLLN
*V0002 X000XXXXXNXLHHLLHLLN
*V0003 X100XXXXXNXHLHLLHLLN
*V0004 X100XXXXXNXHLHLLHLLN
*V0005 X010XXXXXNXLLLLHHLLN
*V0006 X010XXXXXNXLLLLHHLLN
*V0007 X110XXXXXNXLLLHLHLLN
*V0008 X110XXXXXNXLLLHLHLLN
*V0009 X001XXXXXNXLLHLLLLHN
*V0010 X001XXXXXNXLLHLLLLHN
*V0011 X101XXXXXNXLLHLLLHLN
*V0012 X101XXXXXNXLLHLLLHLN
*V0013 X000XXXXXNXLHHLLHLLN
*V0014 X000XXXXXNXLHHLLHLLN
*V0015 X100XXXXXNXHLHLLHLLN
*V0016 X100XXXXXNXHLHLLHLLN
*V0017 X010XXXXXNXLLLLHHLLN
*V0018 X010XXXXXNXLLLLHHLLN

31. 30

*V0019 X110XXXXXNXLLLHLHLLN
*V0020 X110XXXXXNXLLLHLHLLN
*V0021 X000XXXXXNXLHHLLHLLN
*V0022 X000XXXXXNXLHHLLHLLN
*V0023 X100XXXXXNXHLHLLHLLN
*V0024 X100XXXXXNXHLHLLHLLN
*V0025 X010XXXXXNXLLLLHHLLN
*V0026 X010XXXXXNXLLLLHHLLN
*V0027 X110XXXXXNXLLLHLHLLN
* 7D60
4.6 Fuse Plot


**************************************************************************
*****
output
**************************************************************************
*****

CUPL(WM) 5.0a Serial# 60008009
Device g16v8s Library DLIB -h-40-9
Created Mon Mar 04 22:25:25 2013
Name output
Partno 00
Revision 01
Date 03-Mar-13
Designer Engineer
Company Home
Assembly None
Location

==========================================================================
=====
Expanded Product Term s
==========================================================================
=====

U0 =>
Q0 & !Q1 & !Q2

U1 =>
!Q0 & !Q1 & !Q2

U2 =>
!Q1

32. 31


U3 =>
Q0 & Q1

U4 =>
!Q0 & Q1

U5 =>
!Q2

U6 =>
!Q0 & Q2

U7 =>
Q0 & Q2


==========================================================================
=====
Symbol Table
==========================================================================
=====

Pin Variable P terms Max Min
Pol Name Ext Pin Type Used Pterms Level
--- -------- --- --- ---- ------ ------ -----

Q0 2 V - - -
Q1 3 V - - -
Q2 4 V - - -
U0 12 V 1 8 1
U1 13 V 1 8 1
U2 14 V 1 8 1
U3 15 V 1 8 1
U4 16 V 1 8 1
U5 17 V 1 8 1
U6 18 V 1 8 1
U7 19 V 1 8 1


LEGEND D : default variable F : field G : group
I : intermediate variable N : node M : extended node
U : undefined V : variable X : extended
variable
T : function

33. 32

====================================================== ====================
=====
Fuse Plot
==========================================================================
=====

Syn 02192 - Ac0 02193 x

Pin #19 02048 Pol - 02120 Ac1 x
00000 x-------x--------------------- --
00032 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00064 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00096 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00128 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00160 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00192 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00224 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Pin #18 02049 Pol - 02121 Ac1 x
00256 -x------x-----------------------
00288 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00320 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00352 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00384 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00416 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00448 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00480 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Pin #17 02050 Pol - 02122 Ac1 x
00512 ---------x----------------------
00544 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx
00576 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00608 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00640 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00672 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00704 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00736 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x
Pin #16 02051 Pol - 02123 Ac1 x
00768 -x--x---------------------------
00800 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00832 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00864 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00896 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00928 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00960 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00992 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Pin #15 02052 Pol - 02124 Ac1 x
01024 x---x---------------------------
01056 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01088 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01120 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01152 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01184 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01216 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01248 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Pin #14 02053 Pol - 02125 Ac1 x
01280 -----x--------------------------
01312 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01344 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01376 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01408 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx

34. 33

01440 xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
01472 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01504 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Pin #13 02054 Pol - 02126 Ac1 x
01536 -x---x---x----------------------
01568 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01600 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01632 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01664 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01696 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01728 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01760 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Pin #12 02055 Pol - 02127 Ac1 x
01792 x----x---x----------------------
01824 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01856 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01888 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01920 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01952 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01984 xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx
02016 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx


LEGEND X : fuse not blown
- : fuse blown
==========================================================================
=====
Chip Diagram
==========================================================================
=====

______________
| output |
x---|1 20|---x Vcc
Q0 x---|2 19|---x U7
Q1 x---|3 18|---x U6
Q2 x---|4 17|---x U5
x---|5 16|---x U4
x---|6 15|---x U3
x---|7 14|---x U2
x---|8 13|---x U1
x---|9 12|---x U0
GND x---|10 11|---x
|______________|

35. 34

4.7 Results on winsim

36. 35


Fig 4.1 Results onbtained on Winsim
4.8 Hardware Analysis
Initially the debounce switch input is low and T is varied manually. The first
output is that of state S0 that is MG,SR and PR is high.

The last LED will be used for the PG and PY output since the board contain an LED less than the
controller. Then T is set low and state S1 is obtained.
State S1

T is set high and the following output is obtained
State S2

37. 36





T is then set low.
State S3

T is set high
State S0

After this state debounce switch input is set high.
State S1

State S2

State S3

38. 37





State S4

The last LED is representing the PG output and the PY was low when tested.
State S5

Last LED representing PY and PG was low.

The two ICs of 20 pins were placed in the IC test socket of 40 pins. For the first IC, pin number 0
to 10 of the IC test socket represents pin number 0 to 10 of the IC. Pin 31 to 40 of the IC test
socket corresponds to the pin number 11 to 20 of the first IC.

For the second IC pin 1 to 10 corresponds to 11 to 20 of the IC test socket and 11 to 20
corresponds to 21 to 30 of the IC test socket. The table below summarises the pin relationship
between the Ics and the IC test socket.
IC Pins IC test socket Pins
first 1 – 10 1 – 10
11 – 20 31 – 40
second 1 – 10 11 – 20
11 – 20 21 – 30
Table 4.1 Pins relationship between IC and IC test socket

39. 38



APPENDIX
 Datasheets for Quad 2-input AND Gate (74LS08)

40. 39

41. 40

APPENDIX A3
 Datasheet for 3-input AND Gate(74LS11)

42. 41

43. 42

APPENDIX A4
 Datasheet for Dual 4-input AND Gate (74LS21)

44. 43

45. 44

APPENDIX A5
 Datasheet for Quad-2 input OR Gate (74LS32)

46. 45

47. 46

48. 47

49. 48

50. 49


 Datasheet for Quad D flip flop(74LS175)

51. 50

52. 51

53. 52



 Datasheet for gal16v8:

54. 53

55. 54


 Datasheet for NE 555 Timer

56. 55