Unit 2[1] . technology with the informationpptx

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1. Unit 2 Sequential Logic

2. Unit 2 Sequential Logic: Introduction, Types of Seguential circuits Basic storage elements (Latch and Flip-flops), Characteristic equations & tables, excitation table, Flip-flop conversion, Register, Universal Shift register.

3. Sequential Logic Sequential circuits are digital circuits that store and use the previous state information to determine their next state. Unlike combinational circuits, which only depend on the current input values to produce outputs, sequential circuits depend on both the current inputs and the previous state stored in memory elements. Sequential circuits are commonly used in digital systems to implement state machines, timers, counters, and memory elements. The memory elements in sequential circuits can be implemented using flip-flops, which are circuits that store binary values and maintain their state even when the inputs change. There are two types of sequential circuits: finite state machines (FSMs) and synchronous sequential circuits. FSMs are designed to have a limited number of states and are typically used to implement state machines and control systems. Synchronous sequential circuits, on the other hand, are designed to have an infinite number of states and are typically used to implement timers, counters, and memory elements.

4. As shown in the figure, there are two types of input to the combinational logic :  External inputs which are not controlled by the circuit. Internal inputs, which are a function of a previous output state. Secondary inputs are state variables produced by the storage elements, whereas secondary outputs are excitations for the storage elements. 

5. Types of Sequential Circuits: There are two types of sequential circuits:   Type 1:  Asynchronous sequential circuit:   These circuits  do not use a clock signal  but uses the pulses of the inputs. These circuits are  faster  than synchronous sequential circuits because there is clock pulse and change their state immediately when there is a change in the input signal. We use asynchronous sequential circuits when speed of operation is important and  independent  of internal clock pulse.  But these circuits are more  difficult  to design and their output is  uncertain .   

6. Type2:  Synchronous sequential circuit: These circuits  uses clock signal  and level inputs (or pulsed) (with restrictions on pulse width and circuit propagation). The output pulse is the same duration as the clock pulse for the clocked sequential circuits. Since they wait for the next clock pulse to arrive to perform the next operation, so these circuits are bit  slower  compared to asynchronous. Level output changes state at the start of an input pulse and remains in that until the next input or clock pulse.  We use synchronous sequential circuit in synchronous counters, flip flops, and in the design of MOORE-MEALY state management machines. We use sequential circuits to design Counters, Registers, RAM, MOORE/MEALY Machine and other state retaining machines. 

7. Advantages of Sequential Circuits: Memory : Sequential circuits have the ability to store binary values, which makes them ideal for applications that require memory elements, such as timers and counters. Timing : Sequential circuits are commonly used to implement timing and synchronization in digital systems, making them essential for real-time control applications. State machine implementation : Sequential circuits can be used to implement state machines, which are useful for controlling complex digital systems and ensuring that they operate as intended. Error detection : Sequential circuits can be designed to detect errors in digital systems and respond accordingly, improving the reliability of digital systems.

8. Disadvantages of Sequential Circuits: Complexity : Sequential circuits are typically more complex than combinational circuits and require more components to implement. Timing constraints : The design of sequential circuits can be challenging due to the need to ensure that the timing of the inputs and outputs is correct. Testing and debugging : Testing and debugging sequential circuits can be more difficult compared to combinational circuits due to their complex structure and state- dependant outputs.

9. Difference between Flip-flop and Latch S. NO. Flip-flop Latch 1 Flip-flop is a bistable device i.e., it has two stable states that are represented as 0 and 1. Latch is also a bistable device whose states are also represented as 0 and 1. 2 It checks the inputs but changes the output only at times defined by the clock signal or any other control signal. It checks the inputs continuously and responds to the changes in inputs immediately. 3 It is a edge triggered device. It is a level triggered device. 4 Gates like NOR, NOT, AND, NAND are building blocks of flip flops. These are also made up of gates. 5 They are classified into asynchronous or synchronous flipflops. There is no such classification in latches. 6 It forms the building blocks of many sequential circuits like counters. These can be used for the designing of sequential circuits but are not generally preferred. 7 a, Flip-flop always have a clock signal Latches doesn’t have a clock signal 8 Flip-flop can be build from Latches Latches can be build from gates 9 ex:D Flip-flop, JK Flip-flop ex:SR Latch, D Latch

10. Race-round Condition in JK FF If both the  J  and  K  inputs are HIGH at logic “1” (J = K = 1), when the clock input goes HIGH, the circuit will “ toggle ” as its outputs switch and change state complementing each other. This results in the JK flip-flop acting more like a T-type toggle flip-flop when both terminals are “ HIGH ”. However, as the outputs are fed back to the inputs, this can cause the output at  Q  to oscillate between SET and RESET continuously after being complemented once. While this JK flip-flop circuit is an improvement on the clocked SR flip-flop it also suffers from timing problems called “ race ” if the output  Q  changes state before the timing pulse of the clock input has time to go “OFF ”. To avoid this the timing pulse period (  T  ) must be kept as short as possible (high frequency). As this is sometimes not possible with basic JK’s built using basic NAND or NOR gates, far more advanced master-slave (edge-triggered) flip-flops were developed which are more stabe .

11. M aster-Slave (edge-triggered) flip-flops

12. Preset /clear

13. Characteristic equations & tables: RS LATCH

14. 1 1 Characteristic equations & tables: D LATCH

15. Characteristic equations & tables: JK LATCH

16. Characteristic equations & tables: T LATCH

17. Excitation Table and Flip -F lop conversion

18. Conversion of SR FF into D FF

19. Conversion of SR FF into JK FF KQ(t)

20. Conversion of SR FF into T FF

21. Conversion of D FF into JK FF

22. Conversion of D FF into JK FF

23. Shift Registers

24. SISO Shift Registers

25. SIPO Shift Registers

26. PISO Shift Registers

27. PIPO Shift Registers

28. Universal Shift Registers