UNIT 2 8086 System Bus Structure.pptx

Signals, Basic Configurations, I/O Programming, Multiprocessor & Multiprogramming

1. UNIT 2 8086 SYSTEM BUS STRUCTURE 8086 signals – Basic configurations – System bus timing –System design using 8086 – I/O programming – Introduction to Multiprogramming – System Bus Structure – Multiprocessor configurations – Coprocessor, Closely coupled and loosely Coupled configurations – Introduction to advanced processors.

2. 8086 SIGNALS

3. A 40 pin DIP 8086 microprocessor 8086 microprocessor can operate in two modes: Minimum mode and Maximum mode. The pins 24 to 31 have alternate functions for every mode. Minimum mode MN/ MX pin is connected to +5V. Used in small systems including only one CPU. Maximum mode MN/ MX pin is connected to ground. Used in large systems and systems with more than one processor.

4. Address / Data Bus (AD 15 –AD ) The multiplexed Address/ Data bus acts as address bus during the first part of machine cycle (T1) and data bus for the remaining part of the machine cycle. Address/Status (A 19 /S 6 , A 18 /S 5 , A 17 /S 4 , A 16 /S 3 ) During T1 these are the four most significant address lines for memory operations. During I/O operations these lines are LOW. During memory and I/O operations, status information is available on these lines during T2, T3, T WAIT , T4.

5. Bus High Enable/Status ( BHE /S 7 ) During T1 the bus high enable signal ( BHE ) should be used to enable data onto the most significant half of the data bus, pins D 15 ±D 8 . BHE is LOW during T1 for read, write, and interrupt acknowledge cycles when a byte is to be transferred on the high portion of the bus. The S 7 status information is available during T2, T3, and T4.

6. Read ( RD ) This signal is used to read data from memory or I/O device which reside on the 8086 local bus. Ready If this signal is low the 8086 enters into WAIT state. The READY signal from memory/ IO is synchronized by the 8284A clock generator to form READY. This signal is active HIGH. Interrupt Request (INTR) It is a level triggered maskable interrupt request. A subroutine is vectored via an interrupt vector lookup table located in system memory. It can be internally masked by software resetting the interrupt enable bit. INTR is internally synchronized. This signal is active HIGH.

7. TEST This input is examined by the “Wait” instruction. If the TEST input is LOW execution continues, otherwise the processor waits in an ``Idle’’ state. This input is synchronized internally during each clock cycle on the leading edge of CLK. Reset This signal is used to reset the 8086. It causes the processor to immediately terminate its present activity. The signal must be active HIGH for at least four clock cycles. It restarts execution when RESET returns LOW. Clock (CLK) This signal provides the basic timing for the processor and bus controller. The clock frequency may be 5 MHz or 8 MHz or 10 MHz depending on the version of 8086. V CC It is a +5V power supply pin. Ground (GND) Two pins (1 and 20) are connected to ground ie , 0 V power supply. Minimum/Maximum (MN/ MX ) This pin indicates what mode the processor is to operate in. The 8086 can be configured in either minimum mode or maximum mode using this pin.

8. SYSTEM BUS STRUCTURE Microprocessor is processing device of every computing device. It needs to communicate with outer world. It needs to communicate with input devices to get data, it needs to communicate with memory to process data according to instructions written in memory and finally it needs to communicate with output devices to display the output on output devices. To communicate with external world, microprocessor make use of buses. System bus is a single computer bus that connects the major components of a computer system. It consists of data bus, address bus and control bus.

9. Data Bus It is used for the exchange of data between the processor, memory and peripherals. It is bi-directional so that it allows data flow in both directions. The width of the data bus can differ for every microprocessor. When the microprocessor issues the address of the instruction, it gets back the instruction through the data bus. When it issues the address of the data, it loads the data through the data bus.

10. Address Bus The address bus contains the connections between the microprocessor and memory or output devices that carry the signals relating to the addresses which the CPU is processing at that time, such as the locations that the CPU is reading from or writing to. It is unidirectional. The width of the address bus corresponds to the maximum addressing capacity of the bus, or the largest address within memory that the bus can work with. Maximum address capacity = 2 n (n=address lines). Address bus may be multiplexed with data bus.

11. Control Bus The control bus carries the signals relating to the control and coordination of the various activities across the computer, which can be sent from the control unit within the CPU. Microprocessor uses control bus to process data, that is what to do with the selected memory location. Various operations are performed by microprocessor with the help of control bus. This is a dedicated bus, because all timing signals are generated according to control signal Some control signals are Read, Write and Opcode fetch etc.

12. SYSTEM DESIGN USING 8086 The system design starts with specifications. The specification of the system includes the following: I/O devices Memory requirement System clock frequency  Peripheral devices required  Application

13. I/O devices The popular input device used in single board microcomputer system is 8279 – keyboard and display controller. The popular output devices are, LED display LCD Printer Floppy disk / CD CRT terminal Intel 8279 is used for LED display. The LCD and printer are interfaced using ports. Intel 8272 or 82072 floppy disk controller and Intel 8275 CRT controller are popularly used in 8086 system.

14. Memory requirement The memory of the system is splitted between EPROM and RAM. The memory capacity of EPROM and RAM are estimated based on the applications and work to be performed. The popular EPROM used in 8086 based system are 2708 (1K x 8), 2716 (2K x 8), 2732 (4K x 8), 2764 (8K x 8) and 27256 (32K x 8). The popular static RAM used in 8086 based system are 6208 (1K x 8), 6216 (2K x 8), 6232 (4K x 8), 6264 (8K x 8) and 62256 (32 K x 8).

15. System clock frequency The 8086 does not have an internal clock circuit. Hence clock has to be supplied from an external device. The Intel 8284 clock generator is employed to generate the clock. An external quartz crystal has to be connected to 8284 to generate the clock signal. The frequency of quartz crystal should be thrice the internal clock frequency of 8086.

16. Peripheral devices The peripheral devices required for a system depends on its applications. Some of the peripheral devices that can be interfaced to 8086 based system are, Intel 8253 - Programmable Interval Timer Intel 8251 - USART Intel 8255 - Programmable Peripheral Interface Intel 8279 - Keyboard / Display controller Intel 8257 - DMA controller ADC, DAC etc. Application The specifications of the microprocessor itself depends on the applications for the proposed system and the nature of work. The I/O device, memory, peripheral device are all depends on the nature of work to be performed by the system.

17. MIN-MAX MODE OF OPERATION When only 8086 microprocessor is to be used in a microcomputer system, the 8086 is used in the minimum mode of operation. In this mode, the microprocessor issues the control signals required by memory or I/O devices. In a multiprocessor system it operates in the maximum mode . In this mode, the control signals are issued by Intel 8288 bus controller. The pin MN/ MX (33) decides the operating mode of 8086.  When MN/ MX = 0, maximum mode of operation. = 1, minimum mode of operation.  Pins 24 to 31 have different functions for minimum mode and maximum mode.

18. Minimum Mode For minimum mode of operation MN/ MX is connected to V CC (+5 volts).  Pins 24 to 31 have the following functions: Transceivers (8286) – 2 numbers  Clock generator (8284)  Memory or I/O devices.

19. Latches are used for demultiplexing and these latches are enabled by using the ALE signal. 3 numbers of latches (Intel 8282/8283) are used as address latches. The signal DEN is used as an output enable signal.  The signal DT/ R is used as direction control. The clock generator (Intel 8284) does the following functions:  Clock generation  RESET synchronization  READY synchronization Peripheral clock generation HOLD and HLDA signals are used to interface other bus masters like DMA controller. INTA (Interrupt Acknowledge) signal is issued by the microprocessor on receiving any interrupt signal.

20. Maximum Mode For maximum mode of operation MN/ MX pin is grounded.

21. Status signal S2 S1 S0 FUNCTION INTEREUPT ACK 1 I/O READ 1 I/O WRITE 1 1 HLT 1 OPCODE FETCH 1 1 MEMORY READ 1 1 MEMORY WRITE 1 1 1 PASSIVE

22. Maximum Mode – Read Cycle

23. Maximum Mode – Write Cycle

24. I/OPROGRAMMING I/O programming discuss the ways in which information can be transferred between input-output devices or mass storage devices and the CPU or memory. The three modes of transfer of device data, commands and status are, 1.Programmed I/O 2.Interrupt driven I/O 3.DMA Transfer

25. Programmed I/O : The program determines which interfaces need servicing bit testing the ready bits in their status registers. Programmed testing of ready bits or signals is known as polling . Interrupt driven I/O: An external interrupt is sent to the CPU from the interface when the interface has data to input or is ready to accept data and the I/O operation is performed by an interrupt routine. DMA transfer: The interface requests the use of the bus by sending a signal through the control line and makes the necessary transfer without the help of the CPU.

26. PROGRAMMED I /O Read input in programmed I/O mode Programmed I/O consists of continually examining the status of an interface and performing an I/O operation with the interface when its status indicates that it has data to be input or its data-out buffer register is ready to receive data from the CPU.

27. Output write in programmed I/O mode

28. Interrupt driven I /O There are several ways of combining with interrupt I/O, some involving only software, some only hardware, and some a combination of the two. They are, i ) Polling ii) Daisy chaining iii) Interrupt priority management hardware

29. Polling Polling is the most common and simplest method of I/O control. It requires no special hardware and all I/O transfers are controlled by the CPU program. Polling is a synchronous mechanism, by which devices are serviced in sequential order. The polling technique has the following limitations: It is wasteful of the processors time, as it needlessly checks the status of all devices all the time. It is inherently slow When fast devices are connected to a system, polling may simply not be fast enough to satisfy the minimum service requirements

30. Daisy chaining It is a simple hardware means of attaining a priority scheme. It consists of associating a logic circuit with each interface and passing the interrupt acknowledge signal through these circuits as shown in Fig. The priority of an interface is determined by its position on the daisy chain. The closer it is to the CPU the higher its priority. This is significantly faster than a pure software approach. A daisy chain is used to identify the device requesting service.

31. Because more than one device can assert the shared interrupt line simultaneously, some method must be employed to ensure device priority. This is done using the interrupt acknowledge signal generated by the processor in response to an interrupt request. Each device is connected to the same interrupt request line, but the interrupt acknowledge line is passed through each device, from the highest priority device first, to the lowest priority device last. After preserving the required registers, the microprocessor generates an interrupt acknowledge signal. This is gated through each device. If device 1 generated the interrupt, it will place its identification signal on the data bus, which is read by the processor, and used to generate the address of the interrupt-service routine. If device 1 did not request the servicing, it will pass the interrupt acknowledge signal on to the next device in the chain. Device 2 follows the same procedure, and so on.

32. Daisy chaining

33. Interrupt priority management hardware A more flexible hardware priority arrangement can be held by designing a programmable interrupt priority management circuit and including it in the bus control logic. This is the fastest system. The duty is placed on the requesting device to request the interrupt, and identify itself. The identity could be a branching address for the desired interrupt-handling routine. If the device just supplies an identification number, this can be used in conjunction with a lookup table to determine the address of the required service routine. Response time is best when the device requesting service also supplies a branching address.

34. Direct Memory Access Block Transfer A DMA controller allows devices to transfer data to or from the system’s memory without the intervention of the processor. During any given bus cycle, one of the system components connected to the system bus is given control of the bus. Taking control of the bus for a bus cycle is called cycle stealing.

35. MULTIPROGRAMMING Multiprogramming can execute several jobs concurrently by switching the attention of the CPU back and forth among them. This switching is usually prompted by a relative slow input, output storage request that can be handled by a buffer, spooler or channel freeing the CPU to continue processing. The code for two or more processes is in memory at the same time and is executed in a time-multiplexed fashion in multiprogramming. Multiprogramming enable the CPU to be utilized more efficiently. If the operating system can quickly switch the CPU to another task whenever the being worked in requires relatively slow input, output or storage operations, then CPU is not allowed to stand idle.

36. Advantages of multiprogramming It increases CPU utilization.  It decreases total read time needed to execute a job.  It maximizes the total job throughout of a computer. Disadvantages of multiprogramming It is fairly sophisticated and more complex.

37. Process Management

38. MULTIPROCESSOR CONFIGURATIONS A multiprocessor system will have two or more processors that can execute instructions or perform operations simultaneously. Need for Multiprocessor Systems Due to limited data width and lack of floating point arithmetic instructions, 8086 requires many instructions for computing even single floating point operation. For this Numeric Data Processor (8087), can help 8086 processor. Some processor like DMA controllers can help 8086 with low level operations, while the CPU can take care of the high level operations.

39. Advantages It is easy to add more processor for expansion as per requirement.  When a failure occurs, it is easier to replace the faulty processor.  In a multiprocessor system implementation of modular processing of task can be achieved. Basic Multiprocessor Configurations  Co processor configuration  Closely coupled configuration  Loosely coupled configuration

40. COPROCESSOR CONFIGURATION

41. CLOSELY COUPLED CONFIGURATION Coprocessor and closely coupled configurations are similar in that both the 8086 and the external processor (8089) share :  Memory  I/O system  Bus and Bus control logic  Clock generator

42. LOOSELY COUPLED CONFIGURATION In loosely coupled configuration a number of modules of 8086 can be interfaced through a common system bus to work as a multiprocessor system. Each module in the loosely coupled configuration is an independent microprocessor based system with its own clock source, and its own memory and I/O devices interfaced through a local bus. Advantages  Better system throughput by having more than one processor.  The system can be expanded in modular form. Each processor is an independent unit and normally on a separate PC board. One can be added or removed without affecting the others in the system.  A failure in one module normally does not affect the breakdown of the entire system and faulty module can be easily detected and replaced.

43. Bus allocation schemes: Daisy chaining  Polling method  Independent Priority

44. Daisy Chaining

45. Polling Method

46. Independent Priority

47. INTRODUCTION TOADVANCED PROCESSORS

48. Protected mode operation of x86 family

49. Pentium Processors The Pentium family of processors originated from the 80486 microprocessor. The first Pentium processors were introduced in 1993. It runs at a clock frequency of either 60 or 66 MHz and has 3.1 million transistors. The features of Pentium architecture are Improved instruction execution time  Bus cycle pipelining  Address parity .  Internal parity checking  Functional redundancy checking Execution tracing  Performance monitoring  System management mode  Virtual mode extensions

50. The important features of Pentium architecture are Wider (64-bit) Data Bus Superscalar Architecture Dynamic Branch Prediction Logic Enhanced Floating Point Unit Dedicated Instruction and Data Cache Write-Back MESI Protocol in Data Cache

51. Superscalar Architecture of Pentium

52. The Pentium processor has two primary operating modes Protected Mode Real-Address Mode The five stages of Pentium’s basic integer pipeline are, Pre-fetch/Fetch : Instructions are fetched from the instruction cache and aligned in pre-fetch buffers for decoding.   Decode 1 : Instructions are decoded into the Pentium's internal instruction format. Branch prediction also takes place at this stage.   Decode 2 : Same as above, and microcode ROM kicks in here, if necessary. Also, address computations take place at this stage.   Execute : The integer hardware executes the instruction.   Write-back : The results of the computation are written back to the register file.

53. 64-bit processors in personal computers In 1990, IBM introduced microprocessor based on POWER architecture with UNIX operating system. PowerPC was second generation POWER architecture. It has RISC architecture. Design features of PowerPC are as follows. Design features of PowerPC are as follows. Broad range implementation  Simple processor design  Superscalar architecture  Multiprocessor features  64-bit architecture  PowerPC can switch from one mode to another at run time. Separate set of floating point instructions for  Separate set of Floating Point Registers for floating-point instructions

54. Multi-core processor