UNIT 2.pptx

science

1. UNIT 2 Pentium Processor Presented by, Amruta Ingle Assistant Professor, BVUCOEP

2. Pentium Processor Features of Pentium Processor The Pentium family of processors originated from the 80486 microprocessor.  It is an advanced superscalar   32-bit microprocessor , introduced in the year 1993. It contains around 3.1 million transistors. It has a 64-bit data bus and a 32-bit address bus that offers 4 Gb of physical memory space. While the maximum clock rating offered is around 60 to 233 MHz. Multiple Instruction Issue (MII) capability. Pentium processor executes instructions in five stages. This staging, or pipelining, allows the processor to overlap multiple instructions so that it takes less time to execute two instructions in a row. The Pentium processor has two separate 8-kilobyte (KB) caches on chip, one for instructions and one for data. It allows the Pentium processor to fetch data and instructions from the cache simultaneously.

3. Architecture of Pentium Processor

4. Architecture of Pentium Processor

5. Architecture of Pentium Processor The various functional units are as follows : Bus unit Paging unit Code cache Data cache Instruction decode Branch target buffer Prefetch buffer Execution unit with two integer pipeline (U-pipe and V-pipe) Control ROM Dual processing logic Advanced programmable interrupt controller (APIC)

6. Architecture of Pentium Processor BUS UNIT: The bus unit sends the control signal and fetches code and data from external memory and IO devices. The size of the external data bus is 64-bit through which burst read and burst write-back cycles can be achieved. PAGING UNIT: The paging unit in the architecture provides optional extensions of around 2 to 4 Mb page sizes. DATA and CODE CACHE: Both data and code cache within the processor are present. Each cache has 128 sets and each set has 2 lines which are 32 bytes wide. The LRU (Least Recently Used) mechanism handles the cache replacement. The code cache forms a connection with the prefetch buffer by a bus of size 256 bit, thus 256/8 i.e., 32 bytes of opcode can be buffered in one clock cycle. The data cache has two ports that are used to simultaneously deal with two data references.

7. Cache Memory Cache memory is a small-sized type of volatile computer memory that provides high-speed data access to a processor and stores frequently used computer programs, applications and data . Cache memory is the fastest memory available and acts as a buffer between RAM and the CPU . It is the fastest memory in a computer, and is typically integrated onto the motherboard and directly embedded in the processor or main random access memory (RAM ).

8. Cache Memory Cache memory provides faster data storage and access by storing instances of programs and data routinely accessed by the processor. Thus, when a processor requests data that already has an instance in the cache memory, it does not need to go to the main memory or the hard disk to fetch the data. Speed depends on the proximity as well as the size of the cache itself. The more data can be stored into the cache, the quicker it operates

9. Cache Memory

10. Architecture of Pentium Processor In order to load the instructions into the execution unit, code cache , branch target buffer and prefetch buffers operate together. The code cache or the external memory holds the instructions from where these are fetched. Brach Target Buffer: While the branch target buffer holds the address of the respective branch and the TLB (translational lookaside buffer) within the code cache converts the linear address into the physical address that is used by the code cache. Prefetch buffers: This processor contains pairs of prefetch buffers having a size of 32-bytes that combinely operate with branch target buffer (BTB).

11. Architecture of Pentium Processor U and V pipeline : The execution unit within the Pentium microprocessor contains two integer pipelines namely U-pipe and V-pipe and each one has its separate ALU. The U-pipe is responsible for executing all integer as well as floating-point instructions while V-pipe executes simple integer and some floating-point instructions. Control ROM: It directly controls U-pipe and V-pipe.

12. Architecture of Pentium Processor Here, the instruction fetch reads the instruction one at a time and stores them in the instruction queue. During the execution of an instruction, the processor does not sit idle and checks for the next two instructions in the queue. If the two instructions are independent of each other then U-pipe and V-pipe are assigned instructions individually so that execution can occur simultaneously. However, in the case, the queued instructions are dependent on each other then both the instructions are assigned to U-pipe for execution one after the other and V-pipe remains idle.

13. Superscalar Architecture A special category of microprocessors that involves a parallel approach for instruction execution called instruction-level parallelism through which more than one instruction gets executed in one clock cycle is called   superscalar processors . the superscalar processor uses the approach of simultaneously executing two instructions in one clock cycle. The superscalar processors perform this task by sending multiple instructions to various execution units at the same time. Hence this provides high throughput.

14. It is to be noted here that superscalar processors are generally pipelined. However, pipelining is different from super scaling in a way that superscalars allow execution of multiple instructions parallelly using multiple execution units while pipelining uses a single execution unit which is divided into multiple phases in order to execute multiple instructions.

15. Architecture of Pentium Processor Floating Point Unit: There are 8 general-purpose 80-bit Floating point registers. Floating point unit has 8 stages of pipelining. First five are similar to integer unit. Since the possibility of error is more in Floating Point unit (FPU) than in integer unit, additional error checking stage is there in FPU. The floating point unit is shown as below

16. Architecture of Pentium Processor Where, FRD - Floating Point Rounding FDD - Floating Point Division FADD - Floating Point Addition FEXP - Floating Point Exponent FAND - Floating Point And FMUL - Floating Point Multiply