Unit 3 combinational circuits

BCA 121: Computer Organization for BCA(Science) course

1. Computer Organization First Year BCA Science Subject Code : BCA- 121 Subject Teacher : Asst. Prof. Amruta Bhandari

2. COMBINATIONAL CIRCUITS UNIT 3 C O M BIN A T ION A L CIRCUITS 2

3. Combinational Circuits 3 Combinational circuit is a circuit in which we combine the different gates in the circuit, for example encoder, decoder, multiplexer and demultiplexer. Some of the characteristics of combinational circuits are following: Th e o u tp u t o f c om b i n a ti o n a l ci r c u it a t a n y i n s t a n t o f ti m e, d epe n d s o n ly o n the le v els p r es e n t a t i npu t t er m i n als. The combinational circuit do not use any memory. The previousstate of input does not have any effect on the present state of the circuit. A combinational circuit can have an n number of inputs and mnumber of outputs.

4. Block diagram: possible combinations of input values. Specific functions :of combinationalcircuits Adders,subtractors,multiplexers,comprators,encoder,Decoder . M S I Ci r cu i ts a n d s t a nd a r d cells COMBINATIONAL CIRCUITS 4

5. An a l y s i s p r o c edu r e To obtain the output Boolean functions from a logic diagram, proceed as follows: Label all gate outputs that are a function of input variables with arbitrary symbols. Determine the Boolean functions for eachgate output. Label the gates that are a function of input variables and previously labeled gates with other arbitrary symbols. Find the B o o lean f un cti o n s f o r these g a t e s . Repeat the process outlined in step 2 until the outputs of the circuit are obtained. ANA L YSI S PR O C E DURE 5

6. D ESIGN PR O C E D URE 6 Des ig n P r o c edu r e The problem is stated The number of available input variables and requiredoutput v ar i a b l es i s d et er m i n ed. The input and output variables are assigned lettersymbols. The truth table that defines the required relationship betweeninputs and outputs is derived. The simplified Boolean function for each output isobtained. The logic diagram is drawn.

7. BINARY ADDERS 7 ADDERS Half Adder A Half Adder is a combinational circuit with two binary inputs (augends and addend bits and two binary outputs (sum and carry bits.) It adds the two inputs (A and B) and produces the sum (S) and the carry (C) bits. F i g 1:B l o ck d i ag r am F i g 2: T ru t h t a b le S u m = A ′ B + A B ′ = A B Carry=AB

8. Full Adder The full-adder adds the bits A and B and the carry from the previous column called the carry-in C in and outputs the sum bit S and the carry bit called the carry-out C out . BINARY ADDERS 8 Fig 3: block diagram Fig 4:Truth table

9. Half Subtractor A Half-subtractor is a combinational circuit with two inputs A and B a n d t w o o u tp u ts d i f f e r e n c e ( d ) a n d b ar r o w( b ). Fi g 5 : B lock d iag r am Fi g 6: T r u t h t a b le BINARY SUBTRACTORS 9 d= A ′ B + A B ′ = A B b=A′B

10. B I NA R Y SU B T R AC T O R S 10 Full subtractor The full subtractor perform subtraction of three input bits: the minuend , subtrahend , and borrow in and generates two output b its d i f f e r en c e a n d b o r r o w o u t . Fi g 7: Bl o ck d i a g r am F i g 8 : T ru t h t a b le

11. PARALLEL ADDER AND SUBTRACTOR 11 A binary parallel adder is a digital circuit that adds two binary numbers in parallel form and produces the arithmetic sum of those numbers in parallel form Fig 9:parallel adder Fig 10:parallel subtractor

12. CARRY LOOK-A- HEAD ADDER 12 In parallel-adder , the speed with which an addition can be performed is governed by the time required for the carries to propagate or ripple through all of the stages of the adder. The look-ahead carry adder speeds up the process by eliminating this ripple carry delay.

13. CARRY LOOK-A- HEAD ADDER 13 Fi g : 1 bl o ck dia g r am

14. BINARY MULTIPLIER 14 A binary multiplier is an electronic circuit used in digital electronics, such as a computer, to multiply two binary numbers. It is built using binary adders. Example: (101 x 011) Partial products are: 101 × 1, 101 × 1, and 101 ×0 1 1 × 1 1 1 1 1 1 1 1 1 1

15. We can also make an n × m “block” multiplier and use that to form partial products. Example: 2 × 2 – The logic equations for each partial-product binary digit are shown below We need to "add" the columns to get the product bits P0, P1, P2, and P3. BINARY MULTIPLIER 15

16. HA HA A A 1 B 1 B B 1 B BINARY MULTIPLIER 16 P 3 P 2 P 1 P F i g 1 : 2 x 2 m u lti p l i er ar ra y

17. MAGNITUDE COMPARATOR 17 Magnitude comparator takes two numbers as input in binary form and determines whether one number is greater than, less than or equal to the other number. 1 - Bi t Ma g n i t ud e C o m pa r a t o r A comparator used to compare two bits is called a single bit comparator . F i g : 1 Block d ia g r am

18. MAGNITUDE COMPARATOR 18 Fig 2:Logic diagram of 1-bit comparator

19. MAGNITUD E C O M P A R A T O R 19 2 Bit magnitude comparator Fig :3 Block diagram F i g :4 T ru t h t a b le

20. MAGNITUDE COMPARATOR 20 Fig 5:Logic diagram of 2-bit comparator

21. BCD ADDER 21 BCD Adder Perform the addition of two decimal digits in BCD, together with an input carry from a previousstage. When the sum is 9 or less, the sum is in proper BCD form and no correction is needed. When the sum of two digits is greater than 9, a correction of 0110 should be added to that sum, to produce the proper BCD result. This will produce a carry to be added to the next decimal position.

22. D E C ODER 22 A binary decoder is a combinational logic circuit that converts binary information from the n coded inputs to a maximum of 2 n unique outputs. We have following types of decoders 2x4,3x8,4x16…. 2x4 decoder F i g 1 : B l o ck d i ag r am F i g 2: T ru t h t a b le

23. D E CO D E R S 23 H i gh er o r d er d e c o d er i m p le m e n t a t i o n u si n g l o w er o r d e r . Ex :4 x 1 6 d e c o d er usi n g 3 x 8 d e c o d e r s

24. E N CO D E R S 24 An Encoder is a combinational circuit that performs the reverse operation of Decoder. It has maximum of 2 n input lines and ‘n’ output lines. It will produce a binary code equivalent to the input, which is active High . Fig 1:block diagram of 4x2 encoder

25. E N C O D E R S 25 O c t a l t o b i n a r y en c o de r Fig 3: Logic diagram Fig 2:Truth table

26. E N C O D E R 26 Priority encoder A 4 to 2 priority encoder has four inputs Y 3 , Y 2 , Y 1 & Y and two outputs A 1 & A . Here, the input, Y 3 has the highest priority, whereas the input, Y has the lowestpriority. F i g 4: T ru t h t a b le

27. M U L TIP L EX E R S 27 Multiplexer is a combinational circuit that has maximum of 2 n data inputs, ‘n’ selection lines and single output line. One of these data inputs will be connected to the output based on the values of selection lines. We have different types of multiplexers 2x1,4x1,8x1,16x1,32x1…… F i g 1 : Bl o ck d i ag r am F i g 2 : T r u t h t a b le

28. MULTIPLEXERS 28 Fig 3: Logic diagram N o w , l e t u s im p l e m e n t th e h i g h e r - o r d e r Mu l t i p l e x e r u s i n g lo w e r- o r d er Mu l t i p l e x e r s .

29. M U LT I P LE X E R S 29 Ex : 8 x 1 M u lti p l e x e r Fig 3: 8x1 Multiplexerdiagram

30. M U L TIP L EX E R S 30 Implementation of Boolean function using multiplexer f(A1 , A2 , A3 ) =Σ(3,5,6,7) implementation using 8x1 mux

31. M U L TIP L EX E R S 31 f(A1 , A2 , A3 ) =Σ(3,5,6,7) implementation using 4x1 mux Method:1 F i g 1 : T ru t h t a b le

32. MULTIPLEXERS Method:2 F i g 1 : T ru t h t a b le 32

33. DEMULTIPLEXER 33 A demultiplexer is a device that takes a single input line and routes it to one of several digital output lines. A demultiplexer of 2 n outputs has n select lines, which are used to select which output line to send the input. W e h a v e 1 x 2 , 1 x 4 , 8 x 1 … . D e m u lt i p l e x e r s. Fig:1 Block diagram F i g :2 T ru t h t a b le

34. DEMULTIPLEXER 34 B o o lean f un cti o n s f o r each o u tp u t as F ig : 3 L o g ic d ia g r am

35. CODE CONVERTERS 35 A code converter is a logic circuit whose inputs are bit patterns representing numbers (or character) in one code and whose outputs are the corresponding representation in a different code. Design of a 4-bit binary to gray code converter F i g : 1 T r u t h t a b le

36. CODE CONVERTERS K - m ap simp l if i ca ti o n 36

37. COD E C ON V E R T E R S 37 F ig : 2 L o g ic d i a g r am