UNIT III PDF FORMAT 8051 Micrcontroller Akhil.pptx

8051 Microcontroller

1. Unit 3 8051 Microcontroller Prof . Akhil Jaiswal HVPM College of Engineering & Technology 1 Prof. Akhil Jaiswal

2. Unit-III : Introduction to 8051 Microcontroller : 8051 Architecture, 8051 Memory Organization, Registers , Oscillator Unit , Ports, 8051 Interrupt System , Timer units, the Serial Port, 8051 Power Saver Modes. 2 Prof. Akhil Jaiswal HVPM COET

3. Feature set - Does microcontroller support peripherals, I/O port requirements, Sufficient no. of I/O ports, Timers/Counters , ADC/DAC . Speed of Operation - I n terms of Million Instructions Per Seconds. Code Memory Space - Does it support sufficient memory space for hex code. (Program Memory) Data memory Space - Does it support sufficient memory to hold variables & Data structures Development Support – Does provide cost effective development tool, prototype, technical support for Application. Availability- Product development time & Time to market is dependent on Availability, referred as Lead Time Power Concern – Should be minimal and should support Idle and power saver modes. Cost – Should be in reachable limit of end user(Cheaper) 3 Prof. Akhil Jaiswal Factors to be considered in Selection of Microcontroller HVPM COET

4. Features of 8051 Microcontroller An 8051 microcontroller comes bundled with the following features : 6 Interrupts (2 external, 2 timer, 2 serial Interrupts) 16 bit timers/counters 32 I/O lines (4 Ports) 4 k of on chip ROM. 128 bytes on-chip Data M emory (RAM) 128 bytes of Special function registers 32 general purpose registers each of 8-bit 128 user defined software flags 8-bit bidirectional data bus 16-bit unidirectional address bus 16-bit P rogram C ounter and Data P ointer Full duplex UARTs , ADC, Op-amp, etc. 4 Prof. Akhil Jaiswal HVPM COET HVPM COET

5. 5 Prof. Akhil Jaiswal HVPM COET Prof. Akhil M. Jaiswa l

6. 8051 Pin Diagram Prof. Akhil Jaiswal 6 HVPM COET

7. Memory Organisation 8051 is built around HARVAD architecture, program & data memory Program Memory Data Memory Paged Data Memory Von Neumann Memory Model Lower 128 Byte Internal Data Memory (RAM) Upper 128 Bytes RAM (SFRs) Upper 128 Bytes Scratchpad RAM (IRAM) 7 Prof. Akhil Jaiswal HVPM COET

8. Program Memory Provides:- Lowest 4K Bytes of Program Memory as on Chip Switching between internal (up to 0fffh) and External memory is done using External Access(EA\) Pin. Configuring pin enables to access internal memory upto 4K as well as beyond 4K to External Memory . EA\ - 0 enables to External Program code execution Control Signals for external memory execution is PSEN (Program Strobe Enable) 8 Prof. Akhil Jaiswal HVPM COET

9. 8051 Program Memory Organisation External Program Memory (Off chip ROM) FFFFH 0000H External Program Memory (Off chip ROM) Internal Program Memory (On chip ROM) 4K FFFFH FFFFH 0000H 1000H EA\ - 0 (External Program Memory Access) EA\ - 1 (Internal Program Memory Access) 9 Prof. Akhil Jaiswal HVPM COET

10. External Program Memory Interfacing PC Register (16 bit) - PCH (PC higher address) + PCL (PC Lower Address) 8051 P0 ALE Microcontroller (UC) P2 (Program Strobe Enable) PSEN\ ( External Access) EA\ = 0 ( Grnd ) O0.....O7 A0....A7 EXTERNAL Program Memory A8.....A15 OE (Output Enable) Data Bus D0...D7 Address Latch Address Bus Output Enable of ROM Chip 10 Prof. Akhil Jaiswal HVPM COET

11. Data memory (RAM+SFR) Supports- 128 bytes Internal Data Memory- RAM 128 Bytes Special Function registers- IRAM SFRs are Not Available for User Access Interface of 64 kb of external data memory Control lines used are RD\, WR\, PSEN\, ALE\ DPTR is used for storing/giving address with port 0 and port 2 11 Prof. Akhil Jaiswal HVPM COET

12. Data memory (Internal data memory) 12 Prof. Akhil Jaiswal HVPM COET Prof. Akhil M. Jaiswa l

13. External Data Memory Access DPTR Register- DPH (PC higher address) + DPL (PC Lower Address) 8051 P0 ALE P2 P3 RD\ WR\ External Data Memory D0.....D7 A0....A7 A8.....A15 OE (Output Enable) WR\ Data Bus D0...D7 Latch Higher Order Address bus 13 Prof. Akhil Jaiswal HVPM COET`

14. Paged Data Memory Memory is arranged like the lines of Notebook . Notebook may contain 100 to 200 pages and a fixed number of Lines. Can access a specific lines by knowing its page number and line number By using 8 bit of address, memory upto 256 bytes can be accessed 14 Prof. Akhil Jaiswal HVPM COET

15. Von- Neuman Memory Model Code and Data Memory are Combined together Single memory chip can be used with Read/Write options Program Memory is allotted to lower memory space and Data memory to other Specific area Memory Read operations combine with PSEN\ and RD\ signals using AND gate 15 Prof. Akhil Jaiswal HVPM COET

16. Von- Neuman Memory Model 16 Prof. Akhil Jaiswal 8051 P0 MiCr ALE P2 RD\ PSEN\ EA\ WR\ External Memory (Code +Data) D0-D7 A0-A7 A8-A15 OE\ WR\ HVPM COET Prof. Akhil M. Jaiswa l

17. Drawbacks Accidental corruption of Program Memory Reduction of total memory space. Headache to maintaining single memory space for both Program and Data Memory 17 Prof. Akhil Jaiswal HVPM COET

18. Lower 128 Byte Internal Data Memory (RAM) Organisation This memory area is Volatile. The Lowest RAM Contains:- Scratchpad Ram – 80 Bytes General Purpose RD/WR RAM. Bit Addressable Area- 16 Bytes accessed by direct bit addressing useful for Boolean Operation Lowest 32 bytes are grouped into 4 Banks of 8 Registers --R0- R7 for temporary data storage. 18 Prof. Akhil Jaiswal HVPM COET

19. Internal 128 b Lower data memory 19 Prof. Akhil Jaiswal HVPM COET Prof. Akhil M. Jaiswa l

20. Upper 128 Bytes RAM The Upper 128 bytes of Ram when Accessed by Direct Addressing accesses the Special Function Registers. SPRs include port latches, status & control bits, timer control & value registers, CPU registers, SP, accumulators etc. SFRs are both bit-wise and byte-wise accessible. SFR memory is not available to user for general purpose scratchpad RAM usage. 20 Prof. Akhil Jaiswal HVPM COET

21. Upper 128 Bytes IRAM Upper 128 bytes of RAM can be used as general purpose scratchpad RAM by Indirect addressing known as IRAM IRAM address ranges from 80H to FFH Registers R0 and R1 are used for indirect addressing 21 Prof. Akhil Jaiswal HVPM COET

22. Registers Registers can be classified as :- CPU Registers :- Accumulators B Registers Program Status Word (PSW) Data Pointer (DP) Program Counter (PC) Stack Pointer (SP) 2. Scratchpad Registers :- 22 Prof. Akhil Jaiswal HVPM COET

23. CPU Registers Accumulator:- It is the most important CPU register which acts as the heart of all CPU related Arithmetic Operations . Accumulator is an implicit operand in most of the arithmetic operations. Accumulator is a bit addressable register. B Register:- It is a CPU register that acts as an operand in multiply and division operations. it also stores the remainder in division and MSB in multiplication instruction. B can also be used as a general purpose register for programming ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 23 Prof. Akhil Jaiswal HVPM COET

24. PSW.7 PSW.6 PSW.5 PSW.4 PSW.3 PSW.2 PSW.1 PSW.0 CY AC F0 RS1 RS0 OV P 3. Program Status Word:- It is 8 bit, bit addressable special function register signalling the status of accumulator related operations and register Bank selected for the scratchpad registers R0 to R7. BIT NAME EXPLANATION CY Carry Flag Set when a carry on the addition of two 8 bit numbers or when Borrow occurs on the subtraction of two 8 bit numbers AC Auxiliary Carry Flag Sets when carry generated out of bit 3 on addition F0 Flag 0 General Purpose User Programmable Flag OV Over Flow Sets when overflow occurs. P Parity Flag Sets or cleared by hardware is instruction cycle to indicate an odd or even number of 1 in the accumulator PSW.1 General Flag User Programmable general purpose bit RS0 Register Bank Selector 4 Reserved Banks Selector bits RS1 24 Prof. Akhil Jaiswal HVPM COET

25. Reserved Banks Selection RS1 RS0 Register Bank 1 1 1 2 1 1 3 25 Prof. Akhil Jaiswal HVPM COET Prof. Akhil M. Jaiswa l

26. 4. Data Pointer(DPTR):- It is the combination of two 8-bit registers namely DPL(Lower 8-bit holder) & DPH (Higher 8-bit holder). DPTR holds the 16-bit address of the external memory to be read or written in the external data memory operations. 5. Program Counter (PC) :- It is a 16-bit register holding the address of the code memory to be fetched. It is the integral part of the CPU & it is hidden from the programmer. 6. Stack Pointer:- It is an 8-bit register holding the current address of Stack memory, it stores the program counter address, other memory & register values during a Sub Routine call. 26 Prof. Akhil Jaiswal HVPM COET

27. Scratchpad Registers (R0 to R7) It is located in lower 32 bytes of Internal Ram. It can be on of the four Banks which is selected by the register selector bits RS0 & RS1 There are 8 Scratchpad registers R0,R1...R7. Registers R0 to R7 are as a general purpose working registers R7 R6 R5 R4 R3 R2 R1 R0 07H 06H 05H 04H 03H 02H 01H 00H 27 Prof. Akhil Jaiswal HVPM COET

28. Oscillator Unit 28 Prof. Akhil Jaiswal HVPM COET Prof. Akhil M. Jaiswa l

29. 29 Prof. Akhil Jaiswal HVPM COET Prof. Akhil M. Jaiswa l

30. Interrupts Interrupt is something that produces some kind of Interruption. Interrupt is defined as a signal that changes the flow of normal program execution. This Interrupt Signals may come from an Internal/External device needing attention connected to MP/MC. First type of Interrupt signals are referred as External Interrupts 30 Prof. Akhil Jaiswal HVPM COET

31. Why Interrupts? Interrupts are very useful in case to Read/Write some data to an External Device. Without Interrupts normal process apply Polling the device that are of two ways:- Pooling the device continuously - but sacrificing the processor time or system crash Scheduled Pooling on a time slice- but there is also a chance of missing some information from device. 31 Prof. Akhil Jaiswal HVPM COET

32. Uses of Interrupts 32 Prof. Akhil Jaiswal HVPM COET

33. Enabling Interrupts Interrupt System can be enabled or disabled totally under Software Control. This is done by Clearing or Setting a Bit of the SFR Interrupt Enable (IE). IE.7 IE.6 IE.5 IE.4 IE,3 IE.2 IE.1 IE.0 EA RSD RSD ES ET1 EX1 ET0 EX0 33 Prof. Akhil Jaiswal HVPM COET

34. Interrupt Priority Levels INTERRUPT PRIORITY LEVLES External Interrupt 0 Highest Timer 0 overflow Interrupt : : : : External Interrupt 1 Timer 1 overflow Interrupt Serial Interrupt Lowest 34 Prof. Akhil Jaiswal HVPM COET

35. Interrupt Priority IP.7 IP.6 IP.5 IP.4 IP.3 IP.2 IP.1 IP.0 RSD RSD RSD PS PT1 PX1 PT0 PX0 We can set or clear the priority of the interrupts by using an SFR. Interrupt Priority (IP) 35 Prof. Akhil Jaiswal HVPM COET

36. 6. Corresponding Interrupt Service Routine is Executed. 36 Prof. Akhil Jaiswal HVPM COET

37. Timer Units Are very essential for generating precise time reference in any system than can be implemented in S/W of H/W. H/W Timers are dedicated H/W units & are precise in operation. 8051 supports two 16 bit H/W timers that can be configured to operate in either Timer mode or External event Count mode. Timers are named as Timer 0 & Timer 1 that cane be configured as Timer Unit or the Counter Unit by using Timer/Counter Mode Select bit of SFR Timer/ Counter Mode Control (TMOD) 37 Prof. Akhil Jaiswal HVPM COET

38. 1. Timer/Counter Mode Control Register (TMOD) Timer 0 & 1 can operate in Four Modes that can be selected by setting the bit in TMOD reg. Bit Name Description GATE Gating Control Used to Enable the Corresponding Timer/ Counter C/T Counter/ Timer Selector Timer/ Counter mode Select Bit. M1 Mode Select Bits Timer /Counter Operation ‘Mode Select’ Bits (4 Modes) M0 38 Prof. Akhil Jaiswal HVPM COET

39. Timer Modes Mode Select Bits Description M1 M0 Mode 0. 8 bit Timer with divided by 32 prescaler 1 Mode 1. 16 bit Timer 1 Mode 2. Auto-reload Mode. Configures Timer register as 8 bit Timer Counter with Auto reload 1 1 Mode3. Timer 1 in this mode simply holds its Count 39 Prof. Akhil Jaiswal HVPM COET

40. IT1 External Interrupt 1 IT1=1 Configures external Interrupt to edge Trigger IE0 External Interrupt 0 Sets by Hardware when External Interrupt 0 detected IT0 External Interrupt 1 IT1=1 Configures external Interrupt to edge Trigger 40 Prof. Akhil Jaiswal

41. Serial Ports 8051 Supports a Full Duplex, Receive Buffered standard serial interface data transmission. SFR SBUF provides a common interface to both serial reception & transmission registers. Serial communication module contains a Transmit control unit & a Receiver control Unit that are responsible for handling the serial data transmission operations. Serial Port operates in 4 different Modes configured by setting a SFR Serial Port Control (SCON). 41 Prof. Akhil Jaiswal HVPM COET

42. Serial Port Control Register (SCON) SCON.7 SCON.6 SCON.5 SCON.4 SCON.3 SCON.2 SCON.1 SCON.0 SM0 SM1 SM2 REN TB8 RB8 T1 R1 SCON is bit addressable SFR holding the Serial Port Control related bits. Details of SCON are given below:- RB8 - 9 th Data bit received in Mode 2 & 3 Counterpart for RB8. T1 Transmit Interrupt - Set by internal Circuitry at END of Transmission R1 Receive Interrupt - Set by internal Circuitry at END of Reception 42 Prof. Akhil Jaiswal HVPM COET

43. Power Saving Modes Applications Like Battery Operated Systems where power consumption is critical, 8061 provides Power Reduced Modes of Operation:- IDLE Mode POWER DOWN Mode 43 Prof. Akhil Jaiswal HVPM COET

44. 1. IDLE Mode This Mode is activated by setting a bit of a SFR Power Control (PCON) Setting PCON.0 bit Pushes the processor into the IDLE state where the internal Clock of the processor is suspended temporarily. Before putting CPU in idle mode various statuses like Stack Pointer (SP), Program Counter (PC), PSW, Accumulator and other register values are preserved. Interrupt, Timer & Serial port Operates Normal in this Mode. 44 Prof. Akhil Jaiswal HVPM COET

45. PCON Register 45 Prof. Akhil Jaiswal HVPM COET

46. Power Down Mode This Mode is Activated by sitting a bit PCON.1 by an instruction in PCON register. In this mode CPU Stops executing Instructions. Clock signals to all Internal Hardware is Terminated. Contents of Internal RAM & SFRs are Maintained. This mode can only be terminated through H/W reset 46 Prof. Akhil Jaiswal HVPM COET

47. Power Saving Modes Operations 47 Prof. Akhil Jaiswal HVPM COET

48. Question Bank Explain the architecture of the 8051 µc with a Block diagram. Explain the Code & Data memory organization for 8051 for internal and external memory access. Explain Oscillator with Diagram & Machine Cycle details. Explain the memory organization for lower 128 bytes of internal RAM for standard 8051 architecture. Explain All the registers in 8051. (Acc, B, PSW, PC, DPTR, SP, SRF) What is interrupt? What happens when an Interrupt Occurs? Explain IE and IP registers. Explain the timer unit of 8051 architecture along with TMOD and TCON registers. Explain SCON and PCON registers. Prof. Akhil Jaiswal 48 HVPM COET