Unit7_VHDL- VHSIC Hardware Description Language.pptx

VHSIC Hardware Description Language.

1. Introduction to VHDL VHDL = VHSIC Hardware Description Language Used for design, simulation, and synthesis of digital systems Supports Behavioral, Dataflow, Structural modeling Example: entity AND_Gate is Port (A,B: in STD_LOGIC; Y: out STD_LOGIC); end AND_Gate;

2. RTL Design Register Transfer Level → describes data transfer between registers & operations Combinational logic → processes data Sequential logic → uses flip-flops/registers Example: process(clk) if rising_edge(clk) then Q <= D; end if; end process;

3. Combinational Logic Logic without memory → Output depends only on inputs Examples: Adders, Multiplexers, Comparators Example (4:1 MUX): Y <= A when S="00" else B when S="01" else C when S="10" else D;

4. Data Types Scalar types → BIT, BOOLEAN, INTEGER, REAL Composite types → ARRAY, RECORD STD_LOGIC → most widely used Example: signal data_bus : STD_LOGIC_VECTOR(7 downto 0);

5. Operators Logical: and, or, nand, nor, xor Relational: =, /=, <, >, <=, >= Arithmetic: +, -, *, /, mod Example: Z <= (A and B) or (C xor D);

6. Packages Collection of types, constants, functions, procedures Helps reuse code Example: package MyPackage is constant N: integer := 8; end MyPackage;

7. Sequential Circuits Circuits with memory → output depends on present input + past history Built using Flip-flops, Counters, Registers Example (D-Flip Flop): process(clk) if rising_edge(clk) then Q <= D; end if; end process;

8. Subprograms Functions → return a value Procedures → perform a task, may not return Example (Function): function Add_2bit(a,b:STD_LOGIC) return STD_LOGIC is return (a xor b); end function;

9. Example: Adders Half Adder → Sum=A xor B, Carry=A and B Full Adder → 3 inputs Example: S <= A xor B xor Cin; Cout <= (A and B) or (Cin and (A xor B));

10. Example: Counters Binary Counter → Counts up or down Example (4-bit counter): process(clk,reset) if reset='1' then count <= "0000"; elsif rising_edge(clk) then count <= count+1; end if; end process;

11. Example: Flip-Flops D, T, JK Flip-flops modeled in VHDL Example (T-Flip Flop): process(clk) if rising_edge(clk) and T='1' then Q <= not Q; end if; end process;

12. Example: Multiplexers Selects one input out of many Example (2:1 MUX): Y <= A when S='0' else B;

13. Example: Demultiplexers Routes single input to one of many outputs Example (1:4 DEMUX): Y0 <= D when S="00" else '0'; Y1 <= D when S="01" else '0'; Y2 <= D when S="10" else '0'; Y3 <= D when S="11" else '0';

14. Summary VHDL allows design, modeling, and simulation of digital circuits Covers RTL, Combinational & Sequential circuits Includes Operators, Types, Packages, Subprograms Examples: Adders, Counters, Flip-flops, MUX, DEMUX