Universal Chip Interconnect Verification

This presentation introduces a comprehensive verification methodology for Universal Chiplet Interconnect Express (UCIe) technology, addressing the intricate challenges inherent in multi-die system design. Our approach encompasses three critical domains: optimization of multi-die system verification, rigorous validation of automotive-grade UCIe IP, and enhancement of overall verification quality and efficiency.

We demonstrate substantial improvements in verification throughput and silicon quality by employing advanced techniques such as in-depth performance analysis, inter-die transaction integrity verification using a versatile SystemVerilog UVM-based environment. This integrated framework offers a scalable solution to the complex verification challenges presented by chiplet-based architectures, facilitating the development of more robust and efficient semiconductor designs in the post-Moore's Law landscape. We address current industry needs and anticipate future requirements in the evolving field of heterogeneous integration.

1. Beyond Boundaries: Overcoming Chiplet
Verification Challenges
Pankaj Singh [email protected]
Anunay Bajaj [email protected]
Cadence Design Systems, Bangalore, India
© Accellera Systems Initiative 1

2. Agenda
•WHY Chiplet
•Die to Die Verification Challenges and Methodology
–UCIe Die to Die (D2D) System Level Verification
–Automotive Verification
–Execution Efficiency and Quality of Verification
•Conclusion and Benefits
•References
© Accellera Systems Initiative 2

3. Analog/RF and I/O
Cost
The WHYof Chiplets and Multi-Die Packaging
Following Moore’s Law alone is no longerthe best technical/economical path forward
Memory Bandwidth
Size Form Factor and Modularization
Yield
Max reticle limit

4. © Accellera Systems Initiative 4
EFFICIENT VERIFICATION
STRATEGY: MULTI-DIE
SYSTEM
REQURIEMENTS
Build setup for System Performance simulation and Analysis
Latency, Bandwidth
System-level transaction data integrity checks
Identify bottlenecks; provide
feedback to architecture team
for design changes based on
system performance
verification.
Avoided late architecture
changes
EXECUTION
QUALITY AND
QUALITY OF
CHIPLET
VERIFICATION
Reduced Verification
development and debug effort
Overcoming gaps in analog
mixed-signal design
verification for a high-quality
design signoff
HOLISTIC
VERIFICATION
OF UCIe IP:
AUTOMOTIVE
CHALLENGES REQUIREMENTS
SOLUTION/
BENEFITS
Create common verification framework for Automotive
designs:
Preventive monitoring: Registers to capture eye margin
information and per lane error counter with the ability to send
interrupts.
Interoperability, multi-protocol support with a streaming protocol
using the D2D adapter and enabling the co-existence of multiple
protocols.
Mainband (MB) CRC, retry mechanism, and sideband safety
features such as parity, and newly added CRC.
Common setup for the efficient
systematic and functional
safety verification of UCIe PHY IP,
meeting the automotive
verification expectations.
Minimized late design changes due
to issues found later with
automotive verification.
Reduced Verification effort
Develop a scalable, configurable, plug-and-play high-quality
verification environment to support multiple configurations:
IP/Subsystem /Back2Back Chiplet environment.
Designs with single or multiple module (x2, x4) PHY, Adapter
Automotive requirements.
New requirements with incremental spec update : UCIe 1.1/2.0.
Advanced Package (AP)/ Singh Package (SP) designs.
Analog model qualification
Addressing model inaccuracies
AMS Verification Plan (Vplan)

5. © 2024 Cadence Design Systems, Inc. All rights reserved.5
UCIe Die to Die (D2D) System Level Verification

6. System Performance Analysis
System
Verification
Infrastructure
Testbench
Assembly
SoC Tests
libraries
SoC
Performance
analysis
Data / Cache
coherency
checkers
System Performance
Analyzer
System Verification
Scoreboard
Analysis and Checking Generation and Stimulus
System Testbench
Generator
System Traffic
Libraries
Palladium Z1Xcelium Protium X1
FPGA and
Post-Silicon

7. Solution—Complete System Performance and Integrity
Checking
DDR PHY
DDR Ctrl DDR Ctrl
…
DDR PHY
Mesh Interconnect
Snoop Filter
System Cache
Snoop Filter
System Cache
Cluster
Cache
Core Core
Core Core
Cluster
Cache
Core Core
Core Core …
…
DDR PHY
DDR CtrlDDR Ctrl
…
DDR PHY
Mesh Interconnect
Snoop Filter
System Cache
Snoop Filter
System Cache
Cluster
Cache
CoreCore
CoreCore
Cluster
Cache
CoreCore
CoreCore…
…
PCIe
Ctrl
CXL
Ctrl
Stream
Ctrl
UCIe CtrlUCIe Ctrl UCIe Ctrl
UCIe PHY UCIe PHYUCIe PHY
SMMU SMMU
CXL
Ctrl
PCIe
Ctrl
UCIe Ctrl UCIe Ctrl
UCIe PHYUCIe PHY
SMMU SMMU
Stream
Ctrl
UCIe Ctrl
UCIe PHY
System
Scoreboard
(SVD)
System
Performance
Analyzer
(SPA)
Logs
Logs Logs
Logs
Cluster
Cache
Core Core
Core Core
System Libraries
Coherency
PCIe/CXL
Performance
Cluster
Cache
Core Core
Core Core
Coherent
VIP/AVIP
Cache model
translation
Coherent
VIP/AVIP
Cache model
translation
Coherent
VIP/AVIP
Cache model
translation
Coherent
VIP/AVIP
Cache model
translation
Memory VIP/AVIP
(Optional)
Memory VIP/AVIP
(Optional)
Embedded C testsDie 1 Die 2
UCIe Serial Link
Portable
Stimulus
Tests
Identify/Analyze reasons for performance degradation

8. Identifying Performance Bottlenecks
Benefits
✓Insight into relationship
between:
•Bandwidth over time
•Latency over time
•Outstanding transaction
over time
✓Identify/Investigate
bottlenecks
✓Identify outlier
transactions with high
latency and investigate
the time period of
occurrence

9. © 2024 Cadence Design Systems, Inc. All rights reserved.9
Automotive Verification

10. Few Challenges in Automotive
InteroperabilityPreventive Monitoring Functional Safety
ISO 26262

11. UCIe 1.1: Automotive Enhancements and Verification
TheUCIe1.1automotiveenhancementsareallverifiedusingthecommonSV-
UVMtestbench.Theautomotivefeatureverificationincludes:
1.PreventivemonitoringusingregistersaddedinUCIetocaptureeyemargin
informationandperlaneerrorcounterwiththeabilitytosendinterrupts.
2.Interoperability,multi-protocolsupportwithastreamingprotocolusingthe
D2Dadapterandenablingtheco-existenceofmultipleprotocols.
3.Mainband(MB)CRC,retrymechanismandsidebandsafetyfeaturessuchas
parity,andnewlyaddedCRC.
DI E-TO-DI E
ADAPTER
PHYSI CALLAYER
F OR M
FACTOR
PROTOCOL
LAYER
FDI
R a wDie-to-Die Inte rf a ce(RDI)
( Bum ps/Bum pMap)
Sco pe
of
U C Ie
1.1
Specification
PROTOCOL
LAYER
S t a ckMux
Flit-Aw a reDie-to-Die Inte rf a ce(FDI)
Ra wMode
ISO 26262

12. UCIe 1.1: Automotive Enhancements and Verification
✓TheverificationsetupforUCIePHYIPencompassesautomotivesafetyverificationforspecifiedASIL
requirements.
✓FunctionalSafetyverificationisarchitectedalongwithnominalverificationandnotaddedlater.
✓Commonverificationsetupisusedasiswithadditionalconfigurable,lightweighttestcasesforsafety
verification.ThisminimizedchangestotheDesignVerification(DV)environment.
IP
REQ
Customer REQ
App Assumption
FuSA
Concept
FMEA FMEDA
Functional Verification (Systematic)
Digital
P
V
P
L
P
V
S
Design
Update
(Safety
Mech)
✓Architecture→
✓Product→
✓Design
✓FailureModes
✓ASIL REQ
✓FailureMode
→Safety
Mechanism
✓DC(ASIL)
✓PVPL:Product
Verif. Plan
✓Verifiability
✓Verification
Assignment.
✓Verification
Domain
✓PVS: Product
Verif. Spec
✓Verif Strategy
Safety (Random) Verification: Formal/Dynamic
✓Qualitative
Verification
(Fault
injection) of
Safety
Mechanism
✓Functional
Verification
(Systematic)
Closure
Safety
Metric
Verification
Report
✓Statistical
(Fault
injection)
Verification
✓Analysis
SAFETY ANALYSIS/ Fault Optimization
Analog
DESIGN
Fault
Campaign
Mgmt
1
2
3
4
6
5

13. © 2024 Cadence Design Systems, Inc. All rights reserved.13
Execution Efficiency and Quality of Verification

14. DV environment : Configurable Setup
▪Modular setup:
Easy updates .
▪Highly
Configurable
and Scalable
across SP, AP
design flavors.
▪Reusable
across designs
✓Minimizes
development
effort.
✓Promotes focus on
design issues
instead of DV
environment issues
Scoreboard
-Data Comparison Logic
-8 bit Data collection
logic
-Loopback ,lane reversal
scoreboard
Scoreboard
Update for SP
-16bit data collection
support
-Width Degrade
Support
UCIe Testbench
Clock Generator
-Support all clocks
requirement for AP for
various speedmodes
-Quad/Diff Clock
Support
Remote Die Agent
UVC
-Support all features of
AP as remote die
Remote Die Agent UVC
Updates for SP
-Support for SP
Mainband and sideband
-LFSR and serdes updates
-Width Degrade Support
RDI Agent UVC
-Support all features of
AP as local die RDI
interface
RDI Agent UVC
updates for SP
-Support for SP
Mainband and
sideband
-16bit support for SP
Testsuit
-Test suite for all
features of AP
New feature Testsuit for
3,4,5,7 nm
-New tests
features/Customer specific
updates
-Width degrade tests
-FIFO wr/rdcheck tests
Clock Generator
updates
-Lclkchanges for
1Ghz/2Ghz
-Skew and phase shift
updates
-Scaling modes
UCIe Testbench:
Advanced/Standard Package(AP/SP)
AP/ SP :
3,4,5,7nm/
16-32G
Configuration
APB RAL
AP, SP
Sideband
Packet
Decoder
Sideband
Response
Handler
Assertions/Checkers
Assertions/Checkers
-Additional project
specific assertions and
checkers.
Extra
changes
Legacy
blocks AP
Unedited
blocks
Compliance mode
qualification. Interop,
RX EQ
Automotive
New
Updates

15. Design Verification (DV) Environment: PHY IP
Local DIE
UCIe PHY
DUT
Serial
Agent
UVC
Local DIE RDI
Adaptor UVC
CDN APB VIP
Remote DIE UVC
External/Serial IF
Remote
Die LTSM
Model
UVC
SB
Response
Handler
UVC
SERDES
MB UVC
SB
Decoder
UVC
UVM RAL
APB
RDI UVC
RDI
Clock &
Reset Gen
Serial
Agent UVC
MB/SB Scoreboard/ Checkers
▪UCIe PHY DV environment is
decoupled with the design
complexity .
▪The UCIe PHY DV environment
remains similar across AP, SP
designs with common code base
and can be reused across designs
with ease requiring minimal
effort.

16. Unit Level -Physical Layer
Verification Focus
•Detailed Physical Layer Verification
•Handshake with local RDI and remote link partner
•Complexities include Packaging/ Multimodule/ LTSM training , compliance
mode, equalization, automotive and other feature verification
•Physical Layer Sideband and Mainband transactions
•RDI throttling
Verification Components or
Modules
DUT RTL
Legend
D2D
Adapter
RDI
Protocol Layer
FDI
Streaming
PCIe
CXL
FDI
UCIe MultiprotocolPartial Stack Simulation or
Emulation Verification Components
Testbench
Logs
Link
Monitors
Mainband
Serial
Sideband
Serial
Physical
Layer
Physical
Layer
DUT
D2D
Adapter
Protocol Layer
Streaming
PCIe
CXL
RDI
User Tests
UCIe MultiprotocolFull Stack Simulation or
Emulation Verification Components
UCIe PHY DUT
Link
Monitors
Standalone IP Verification

17. PHY M0
PHY M1
MMPL
UCIe X2 Local Die (DUT)
RDI UVC Agent
Serial UVC Agent 0
Serial UVC Agent 1
RDI If –
MB/SB
Serial If M1 –
MB/SB
MMPL
Virtual
Sequence
Wrapper
MB Scoreboard –Byte Mapping
Serial If M0 –
MB/SB
APB UVC Master APB IF
RAL Model
Top MMPL CFG
CFG M0
CFG M1
Clock Generator
Assertions & Coverage
Testbench Top
Testbench
Components
UVM Agents
Sequences
DUT
Remote Die UVC
Multi-Module Testbench configuration
X1, X2 and X4
scalable testbench

18. ✓AXI Controller UVC is used.
✓Back2Back setup is used in
Subsystem DV.
✓PHY IP DV, Controller IP:
Done in standalone IP
verification.
✓Subsystem (SS) DV focus
on Subsystem integration,
data integrity for all
modes.
Sample Multi Module Verification : AXI mode

19. Verification Areas –Leverage Multiple Technologies
UCIe PHY
PCIe Ctrl
SMMU
DDR PHY
DDR Ctrl DDR Ctrl…
DDR PHY
Mesh Interconnect
Snoop Filter
System Cache
Snoop Filter
System Cache
Cluster
Cache
Core Core
Core Core
Cluster
Cache
Core Core
Core Core
Cluster
Cache
Core Core
Core Core…
…
UCIe Ctrl
UCIe PHY
CXL Ctrl
SMMU
UCIe Ctrl
UCIe PHY
Stream
Ctrl
UCIe Ctrl
UCIe Digital Interface
Verification
PCIe/CXL with integral UCIe
Verification
PCIe/CXL System Integration
Verification and Performance
Streaming Coherency
Verification and Performance
UCIe Protocol Compliance
Protocol + functional behavior
correctness
Cache coherency, Address Map
correctness, Latency/bandwidth
Realistic workload performance
DVM Traffic, DDR/UCIe
performance
Topologies Verification focus

20. Verification Quality: AMS Vplan
SNo Features/Functions MLM Switches Description
1
DCC
DV_TX/RX_CLOCK/VALID/DATA*_EN_DUTY_DISTORT,
DV_TX/RX_CLOCK/VALID/DATA*_DUTYCYCLE_TARGET
Generate distortion on the TX side.
Apply Duty Cycle Distortion on the TX, RX side of EXT interface
2
DESKEW
DV_TX_CLOCK/VALID/DATA*_DESKEW_CAL_TARGET
RX_SKEWON
Generate distortion on the TX side
Apply Skew on the TX and RX side of EXT interface
3
PLL
DV_CMN_BANDGAP_CODE
DV_CMN_VCOCAL_CODE
Apply offset to verify bandgap calibration
Apply offset to verify VCO calibration
Note:
1. Separate AMS Vplan tracking jira will be used for review/closure
2. VCD based approach used to uncover system level issues between analog-digital boundaries

21. © 2024 Cadence Design Systems, Inc. All rights reserved.21
Conclusion and Benefits

22. Conclusion and Benefits
© Accellera Systems Initiative 22
Performance Verification
Verification Efficiency
Verification Quality

23. References
[1]An Approach to Overcome Modeling Inaccuracies for Performance Simulation Signoff of
High-Speed SerDes.
[2]Overcoming challenges of verifying complex mixed signal designs.
[3]UCIe™specification.
Thank you
Thanks to Cadence D2D Verification team for their contributions in building a verification
environment for UCIe programs.

24. Questions
© Accellera Systems Initiative 24

25. © 2022 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and the other Cadence marks found at www.cadence.com/go/trademarksare trademarks or registered trademarks of Cadence Design
Systems, Inc. Accellera and SystemCare trademarks of Accellera Systems Initiative Inc.All Arm products are registered trademarks or trademarks of Arm Limited (orits subsidiaries) in the US and/or elsewhere. All MIPI
specificationsare registered trademarks or service marks owned by MIPI Alliance.All PCI-SIG specificationsare registered trademarks or trademarks of PCI-SIG. All other trademarks are the property of their respective owners.