Verilog-Behavioral Modeling .pdf

Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL). It is a language used for describing a digital system like a network switch or a microprocessor or a memory or a flip−flop. It means, by using a HDL we can describe any digital hardware at any level. Designs, which are described in HDL are independent of technology, very easy for designing and debugging, and are normally more useful than schematics, particularly for large circuits.

Verilog supports a design at many levels of abstraction. The major three are −

Behavioral level
Register-transfer level
Gate level
Behavioral level
This level describes a system by concurrent algorithms (Behavioural). Every algorithm is sequential, which means it consists of a set of instructions that are executed one by one. Functions, tasks and blocks are the main elements. There is no regard to the structural realization of the design. Verilog Keywords
Words that have special meaning in Verilog are called the Verilog keywords. For example, assign, case, while, wire, reg, and, or, nand, and module. They should not be used as identifiers. Verilog keywords also include compiler directives, and system tasks and functions.

Gate Level Modelling
Verilog has built-in primitives like logic gates, transmission gates and switches. These are rarely used for design work but they are used in post synthesis world for modelling of ASIC/FPGA cells.

Gate level modelling exhibits two properties −

Drive strength − The strength of the output gates is defined by drive strength. The output is strongest if there is a direct connection to the source. The strength decreases if the connection is via a conducting transistor and least when connected via a pull-up/down resistive. The drive strength is usually not specified, in which case the strengths defaults to strong1 and strong0.

Delays − If delays are not specified, then the gates do not have propagation delays; if two delays are specified, then first one represents the rise delay and the second one, fall delay; if only one delay is specified, then both, rise and fall are equal. Delays can be ignored in synthesis.

Gate Primitives
The basic logic gates using one output and many inputs are used in Verilog. GATE uses one of the keywords - and, nand, or, nor, xor, xnor for use in Verilog for N number of inputs and 1 output.

1. Digital System Design
-Behavioral Modeling
Prof. Dhaval shah

2. Objectives of this Topic
•initial and alwaysblocks
•The concept of multiple flows of control
•Practice simple examples
•Proceduralassignment vs. Continuous assignment
•Blocking vs. non-blocking assignments
•Conditional statements
–if, case, casex, casez
•Loop statements
–while, for, repeat, forever

3. Introduction
•Themovetowardhigherabstractions
–Gate-levelmodeling
•Netlistofgates
–Dataflowmodeling
•Booleanfunctionassignedtoanet
–Now,behavioralmodeling
•Asequentialalgorithm(quitesimilartosoftware)that
determinesthevalue(s)ofvariable(s)
2010 3

4. Structured Procedures
•Two basic structured procedure statements
always
initial
–All behavioral statements appear only inside these blocks
–Each always or initial block has a separate activity flow
(multithreading, concurrency)
–Start from simulation time 0
–No nesting

5. Structured Procedures:
initialstatement
•Starts at time 0
•Executes only once during a simulation
•Multiple initialblocks, execute in parallel
–All start at time 0
–Each finishes independently
•Syntax:
initial
begin
// behavioral statements
end
DSD 5

6. Structured Procedures:
initialstatement (cont’d)
module stimulus;
reg x, y, a, b, m;
initial
m= 1’b0;
initial
begin
#5 a=1’b1;
#25 b=1’b0;
end
initial
begin
#10 x=1’b0;
#25 y=1’b1;
end
initial
#50 $finish;
endmodule
DSD 6
Example:

7. Initializing variables
•Ordinary style, using initialblock
reg clock;
initial clock = 0;
•Combined declaration and initialization
reg clock = 0; // RHS must be constant
module adder (
output reg [7:0] sum = 0,
output reg co = 0,
input [7:0] a, b,
input ci);
...
endmodule
7DSD

8. Structured Procedures:
alwaysstatement
•Start at time 0
•Execute the statements in a looping fashion
module clkgen ( output reg clock);
Initial
clock = 1’b0;
Always
#10 clock = ~clock;
Initial
#1000 $finish;
...
endmodule
DSD 8

9. Procedural Assignments
•Assignments inside initialand always
•To update values of “register, integer, real or
time” variables.
–The value remains unchanged until another
procedural assignment updates it
DSD 9

10. Procedural Assignments (cont’d)
•Syntax
<lvalue> = <expression>
–<lvalue>can be
•reg, integer, real, time
•A bit-select of the above (e.g., addr[0])
•A part-select of the above (e.g., addr[31:16])
•A concatenation of any of the above
–<expression>is the same as introduced in dataflow modeling
–What happens if the widths do not match?
•LHS wider than RHS => RHS is zero-extended
•RHS wider than LHS => RHS is truncated (Least significant part is kept)
DSD 10

11. Blocking Procedural Assignments
•The two types of procedural assignments
–Blocking assignments
–Non-blocking assignments
•Blocking assignments
–are executed in order (sequentially)
–Example:
reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count;
initial begin
x=0; y=1; z=1;
count=0;
reg_a= 16’b0; reg_b = reg_a;
#15 reg_a[2] = 1’b1;
#10 reg_b[15:13] = {x, y, z};
count = count + 1;
end
DSD 11
All executed at time 0
All executed at time 25
executed at time 15

12. Non-Blocking Procedural Assignments
•Non-blocking assignments
–Processing of the next statements is not blockedfor this one
–Transactions createdsequentially (in order), but executed after all
blocking assignments in the corresponding simulation cycle
–Syntax:
<lvalue> <=<expression>
–Example:
reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count;
initial begin
x=0; y=1; z=1;
count=0;
reg_a= 16’b0; reg_b = reg_a;
reg_a[2] <= #15 1’b1;
reg_b[15:13] <= #10 {x, y, z};
count <= count + 1;
end
All executed at time 0
Scheduled to run at time 15
Scheduled to run at time 10

13. Non-Blocking Assignments (cont’d)
•Application of non-blocking assignments
–Used to model concurrent data transfers
–Example: Write behavioral statements to swap values of two
variables
always @(posedge clock)
begin
reg1 <= #1 in1;
reg2 <= @(negedge clock) in2 ^ in3;
reg3 <= #1 reg1;
end
DSD 13
The old value of reg1 is used

14. Cont..
•When the final result of simulating two (or more)
concurrent processes depends on their order of execution
•Example:
always @(posedge clock)
b = a;
always @(posedge clock)
a = b;
•Solution:
always @(posedge clock)
b <= a;
always @(posedge clock)
a <= b;
DSD 14
always @(posedge clock)
begin
temp_b = b;
temp_a = a;
b = temp_a;
a = temp_b;
end

15. Conditional Statements
Multiway Branching

16. Behavioral Modeling Statements:
Conditional Statements
•Just the same as if-elsein C
•Syntax:
if (<expression>)true_statement;
if (<expression>)true_statement;
elsefalse_statement;
if (<expression>)true_statement1;
else if (<expression>)true_statement2;
else if (<expression>)true_statement3;
elsedefault_statement;
•Trueis 1or non-zero
•Falseis 0or ambiguous (xor z)
•More than one statement: begin end

17. Behavioral Modeling Statements:
Multiway Branching
•Similar to switch-casestatement in C
•Syntax:
case (<expression>)
alternative1: statement1 ;
alternative2: statement2 ;
...
default:default_statement; // optional
endcase
•Notes:
–<expression> is compared to the alternativesin the order
specified.
–Default statement is optional
2010 DSD 18

18. Multiway Branching (cont’d)
•The casestatements compare <expression> and alternatives bit-for-bit
–xand zvalues should match
2010 DSD 19
module demultiplexer1_to_4(out0, out1, out2, out3, in, s1, s0);
output out0, out1, out2, out3;
input in, s1, s0;
always @(s1 or s0 or in)
case( {s1, s0} )
2’b00: begin ... end
2’b01: begin ... end
2’b10: begin ... end
2’b11: begin ... end
2’bx0, 2’bx1, 2’bxz, 2’bxx, 2’b0x, 2’b1x, 2’bzx:
begin ... end
2’bz0, 2’bz1, 2’bzz, 2’b0z, 2’b1z:
begin ... end
default: $display(“Unspecified control signals”);
endcase
endmodule

19. Multiway Branching (cont’d)
•casexand casezkeywords
–caseztreats all zvalues as “don’t care”
–casextreats all xand zvalues as “don’t care”
2010 DSD 20

20. Behavioral Modeling Statements: Loops
•Loops in Verilog
–while, for, repeat, forever
•The while loop syntax:
while (<expression>)
statement;
2010 DSD 21

21. Loops (cont’d)
•The forloop
–Similar to C
–Syntax:
for( init_expr; cond_expr; change_expr)
statement;
2010 DSD 22

22. Loops (cont’d)
•The repeatloop
–Syntax:
repeat( number_of_iterations )
statement;
–The number_of_iterations expression is evaluated only
when the loop is first encountered
integer count;
initial
begin
count = 0;
repeat(128) begin
$display("Count = %d", count);
count = count + 1;
end
end
2010 23

23. Loops (cont’d)
•The foreverloop
–Syntax:
forever
statement;
–Equivalent to while(1)
2010 DSD 24

24. Timing Controls in
Behavioral Modeling

25. Introduction
•No timing controls No advance in simulation time
•Three methods of timing control
–delay-based
–event-based
–level-sensitive
2010 DSD 26

26. Delay-based Timing Controls
•DelayDuration between encountering and
executing a statement
•Delay symbol: #
•Delay specification syntax:
#5
#(1:2:3)
2010 DSD 27

27. Delay-based Timing Controls (cont’d)
•Types of delay-based timing controls
1. Regular delay control
2. Intra-assignment delay control
3. Zero-delay control
2010 DSD 28

28. Regular Delay Control
•Symbol: non-zero delay beforea procedural assignment
2010 DSD 29

29. Intra-assignment Delay Control
•Symbol: non-zero delay to the rightof the
assignment operator
•Operation sequence:
1. Compute the RHS expression at current time.
2. Defer the assignment of the above computed
value to the LHS by the specified delay.
2010 DSD 30

30. 02/18/17 Vijay Savani @ 2016
Intra-assignment Delay Control

31. Zero-Delay Control
•Symbol: #0
•Different initial/alwaysblocks in the same simulation
time
–Execution order non-deterministic
•#0 ensures execution after all other statements
–Eliminates race conditions (only in simulation)
•Multiple zero-delay statements
–Non-deterministic execution order
2010 DSD 32

32. Zero-Delay Control
2010 DSD 33

33. Event-based Timing Control
•Event
–Change in the value of a register or net
–Used to trigger execution of a statement or block
(reactive behavior/reactivity)
•Types of Event-based timing control
1. Regular event control
2. Named event control
3. Event OR control
2010 DSD 34

34. Regular Event Control
•Symbol: @(<event>)
•Events to specify:
–posedge sig
•Change of sigfrom any value to 1
or from 0 to any value
–negedge sig
•Change of sigfrom any value to 0
or from 1 to any value
–sig
•Any change in sigvalue
2010 DSD 35

35. Named Event Control
•You can declare(name) an event, and then trigger
and recognize it.
•Keyword: event
event calc_finished;
•Verilog symbol for triggering: ->
->calc_finished
•Verilog symbol for recognizing: @()
@(calc_finished)
2010 DSD 36

36. Named Event Control
2010 DSD 37

37. Event OR control
•Used when need to trigger a block upon occurrence
of any of a set of events.
•The list of the events: sensitivity list
•Keyword: or
•Simpler syntax
–always @( reset, clock, d)
2010 DSD 38

38. Event OR control
•Simpler syntax
–@* and @(*)
•OR
2010 DSD 39

39. Level-sensitive Timing Control
•Level-sensitive vs. event-based
–event-based: wait for triggering of an event
(change in signal value)
–level-sensitive: wait for a certain condition (on
values/levels of signals)
•Keyword: wait()
always
wait(count_enable) #20 count=count+1;
2010 DSD 40

40. Have you learned this topic?
•Race conditions
–Blocking vs. non-blocking assignments
–Zero delay control
•Timing control in behavioral statements
–Required to advance the simulation time
–Different types
•Delay-based
•Event-based
•Level-sensitive
2010 DSD 41

41. Objectives of This Topic
•Some more constructs on Behavioral
Modeling
–Parallel blocks
–Nested blocks
–disable keyword
•Verilog® Scheduling Semantics
2011 DSD 42

42. Blocks, Sequential blocks
•Used to group multiple statements
•Sequential blocks
–Keywords: begin end
–Statements are processedin order.
–A statement is executedonly after its preceding
one completes.
•Exceptions: non-blocking assignments and
intra-assignment delays
–A delay or event is relative to the simulation time
when the previous statement completed
execution
2011 DSD 43

43. Parallel Blocks
•Parallel Blocks
–Keywords: fork, join
–Statements in the blocks are executed concurrently
–Timing controls specify the order of execution of the
statements
–All delaysare relative to the time the block was entered
•The written order of statements is not important
•The joinis done when all the parallel statements are finished
2011 DSD 44

44. Sequential vs. Parallel Blocks
initial
begin
x=1’b0;
#5y=1’b1;
#10z={x,y};
#20w={y,x};
end
initial
fork
x=1’b0;
#5y=1’b1;
#10z={x,y};
#20w={y,x};
join
DSD 452011

45. Parallel Blocks and Race
•Parallel execution Race conditions may arise
initial
fork
x=1’b0;
y=1’b1;
z={x,y};
w={y,x};
join
•z,wcan take either 2’b01, 2’b10
or 2’bxx, 2’bxx or other combinations
depending on simulator
2011 DSD 46

46. Special Features of Blocks
•Contents
–Nested blocks
–Named blocks
–Disabling named blocks
2011 DSD 47

47. Nested Blocks
•Sequential and parallel blocks can be mixed
initial
begin
x=1’b0;
fork
#5 y=1’b1;
#10 z={x,y};
join
#20w={y,x};
end
2011 DSD 48

48. Named blocks
•Syntax:
begin: <the_name> fork: <the_name>
… …
end join
•Advantages:
–Can have local variables (local variables are static)
–Are part of the design hierarchy.
–Their local variables can be accessed using hierarchical
names
–Can be disabled
2011 DSD 49

49. Disabling Named Blocks
•Keyword: disable
•Action:
–Similar to breakin C/C++, but can disable any
named block not just the inner-mostblock.
2011 DSD 50

50. Functions and Task
2010 DSD 51

51. Introduction
•Procedures/Subroutines/Functions in SW
programming languages
–The same functionality, in different places
•Verilog equivalence:
–Tasksand Functions
–Used in behavioral modeling
–Task and functions can not have wires and contain
behavioral statements only.
2010 DSD 52

52. Differences between...
•Functions
–Canenable(call)justanother
function(nottask)
–Executein0simulationtime
–Notimingcontrolstatements
allowed
–Atleastoneinput
–Return only a single value
–UsedwhenVerilogcodeispurely
combinational,executeinzero
simulationtimesandprovides
exactlyoneoutput
•Tasks
–Canenableothertasksandfunctions
–Mayexecuteinnon-zerosimulation
time
–Maycontainanytimingcontrol
statements
–Mayhavearbitraryinput,
output,orinout
–Donotreturnanyvalue
–UsedforVerilogcodethatcontains
delays,timing,eventconstructs,
eventconstructsormultipleoutput
arguments
2010 DSD 53

53. Functions
•Keyword: function, endfunction
•Can be used if the procedure
–does not have any timing control constructs
–returns exactly one single value
–has at least one input argument
2010 DSD 54

54. Function Declaration Syntax
function<range_or_type> <func_name>;
input<input argument(s)> // at least one input
<variable_declaration(s)> // optional
begin // if more than one statement needed
<statements>
end// if begin used
endfunction
2010 DSD 55

55. Function Examples: Parity Generator
2010 DSD 56
Function that calculates the parity of a 32-bit address and returns the value

56. Function Semantics
–much like functionin Pascal
–An internal implicit regis declared inside the
function with the same name
–The return value is specified by setting that
implicit reg
–<range_or_type>defines width and type of
the implicit reg
•<type>can be integeror real
•default bit width is 1
2010 DSD 57

57. Tasks
•Keywords: task, endtask
•Mustbe used if the procedure has
–any timing control constructs
–zero or more than one output arguments
–no input arguments
2010 DSD 58

58. Task Declaration Syntax
task<task_name>;
<I/O declarations> // optional
<variable and event declarations>
begin// if more than one statement needed
<statement(s)>
end // if beginused!
endtask
2010 DSD 59

59. Task Invocation Syntax
<task_name>;
<task_name> (<arguments>);
–inputand inoutarguments are passed into the
task
–outputand inoutarguments are passed back
to the invoking statement when task is completed
2010 DSD 60

60. I/O declaration in modules vs. tasks
–Both use keywords: input, output, inout
–In modules, represent ports
•connect to external signals
–In tasks, represent arguments
•pass values to and from the task
2010 DSD 61

61. Task Examples
2010 DSD 62

62. Other way to define task
2010 DSD 63

63. Automatic Tasks and Functions
•Used for re-entrant code
–Task called from multiple locations
–Recursive function calls
•Keyword
–automatic
•Example
function automatic integer factorial;
task automatic bitwise_xor;
2010 DSD 64