verilog modelling and types of modellings

“A stick diagram is a cartoon of a layout.”
The designer draws a freehand sketch of a layout, using colored lines to represent the various
process layers such as diffusion, metal and polysilicon. Where polysilicon crosses diffusion,
transistors are created and where metal wires join diffusion or polysilicon, contacts are formed.
For example, in the case of nMOS design,
 Green color is used for n-diffusion
 Red for polysilicon
 Blue for metal
 Yellow for implant, and black for contact areas.
Monochrome encoding is also used in stick diagrams to represent the layer information.

1. Samir Palnıtkar

2. is in behavioral modeling
Other statements can appear only inside th
blocks:
always and Initial rept
flow

Both blocks begin

3. initial
> Starts at zero simulation time

»executes only once during a simulation
> All initial blocks executed concurrently at
time 0)

> begin-end is used to build initial blocks
(similar to {-} in C)

» Used mainly for initialization, monitoring
and waveforms and other processes that
must be executed only once during the
entire simulation run

Ir. ra
EEE/CSC-273

4. multiple:
neea Ton

endmodule

5. Example-7.1 : initi

nent E
i= 1490;
= lot;
x = 1/00;
b)= 1/0;

"bi;

6. always

ation time
ously In a looping

ea
ock of activity that | ish
sly in a digital circuit

ised to, build initial block
in O)

n ©)

8. Y

Procedural Assignment

a procedural assignment
of the following:
| or time register variable or a memory

9. Blocking) assignments

tia block

ssignmen En
> Use blocking statements to build
combinational logic block

11. Non-blocking assignments

> Allows scheduling of assignments without
blocking) execution of the statements that
follow in a sequential block

> A” <= * operator is used to specify non-

blocking assignments
» Executed last in the time step in which they
are scheduled, that is, after all the blocking
assignments in that time step are executed
» Use non-blocking statements to build
Sequential loaic block

12. nple

module dummy;

nteger count;

(Ail behavioral) emenis must beinside
//Dont mix blocking and non-blocking sta
initié

ent with delay (@time 15)

[ (@tim

$monitor(s

13. Application of non-blocking
assignments

> They are use

concurrent dat

a met ps to model
that take ola

alter a common eve

» Disadvant
performal

tion in the simu
in memory

14. n-blocking a

Begin

At each positive edge of clock following) si

non-blocki

ions are exect

Ihe order in which the write operations are exec!

important.

15. - 7.5 ; non-blocking statements to elimin:
On Ie WwWo eonetirron: always blocksiwiihrblockIng

@(posedge clock),

bs

ways @(posedge

ion 27 TWO Concurrent always blocks with nonnlock:
ements:

s @(posedge clock)

by

Ways @(posedge clock),

16. f non-blockin

lways @(posedge clock)
begin
Read OpeTranion

Of Gint-WanG-Side Expressions ii)

ANTE Operation)

///ASsign) Values oí temporary Variables to left-hand-side variables:

lemp_b;

temp_a;

17. Timing Control for Simulation

> lí no timing control statement,
simulation time does not advancı

Delay based timing control
Event based timing control

18. based timing control

e duration between when!

tne
3 encountered) and when It Is

# <number>

#<identifier>

# (minimum: typical:

maximum)

19. Example

Regular delay contro).

when the
Encountered

1 AO JUN its,
Ol

Minimum
1/3

20. 1e right of
gnment operator

3101 x and at the |= 0) evaliiate x.
Walt SMe Units tO assign Value toy

with) temporany Variables and reguiar a

21. [always or
same

A IS
on time,

22. zero delay contro!

zero delay contro)

23. control

an event... 2

ange in the value of a register or a net

[control
rol

+ ar event contre
= Named) event control

= Event or un

=

24. le valu
legative tra nsiti

Ver SiGiiall Clock

ion ( 0 to 1, x of zZ,

Ver signal clock
(1 to 0, xt

26. event OR control

> Transition on any one of multiple signals or events

always @(reset or clock or D)
begin
it(reset)
q = 10;
else ¡f(clock)

q= D;

27. Level sensitive

yeti is level sen: Ena
= Waits for

block Is

always
wait (count_enable) #20 count = count + 1;

ANNO MOS CONLINUEUSIY

29. = queued < MAX_Q_ DEPTH)

number_queued

Types

[Execute ski

if (alu_control
X + Z;

ui control

rol signal”)

30. // lock of statement

(pression and ihe
equal bit width, th

At h the widest Ban,

31. imple 7.14 : multiple
nodule mi

ROT
output out
nput iO,
nput si, sO;

reg out;

or SO or i0 or i2 or i
x ih) Of; como)

Switch k

control sig)

endmodule

32. eg) outdo,

any)

33. Example 7.15 tatement with x and z continue.

module stimulus;

IN, S

$monitor($time
OUTO, OU
initia

beg

35. Le
Loops
Ops

ession>)
Man
y logic
Xpress

36. module counter;

integer count;

37. xed number of times
a number (constant, variable, signal value)
Î alue evaluated only when

ment and alsplay/c

38. ning const
o gen

ple 7.20)

39. tements are processe: the order they are specifiec
y/ever r to the simulation time when the
VIOUS ste the block completed execution

= Example

//MuUstravion) iz Sequential block without delay,

40. xample 7

z= %b, w= %b\n", x, y, Z, W);

// complet

// Completes at simu
// Competes at; simu
// complet i

41. D.

Parallel blocks

>

Blocs with) d

42. kg
CS,

#20 w = {y, x};

end)

endmodule

43. Named Block

ed, i.e. their execution can be

avale i iat

9) Count

6'b 0010_0000_0001 ;
begin: block1 he main n while is named block:

44. Example (traffic signal controller)

46. venlos description

47. I 7 Al
Ip
8
= GOeESC
les
A
0)
: tive
E
aa

age)

48. Verilog description (cont...)

49. Verilog

entry = %b",

50. Verilog description (Stimulus)