Vlsi design 11

Vlsi design introduction

1. MVLSI Design MR. HIMANSHU DIWAKAR Assistant Professor JETGI MR. HIMANSHU DIWAKAR JETGI 1

2. MR. HIMANSHU DIWAKAR JETGI 2 Intel processor

3. Think about it… On previous slide we see a picture that is the processor of computer and the image is from Intel lab. The zooming size is of scale of rabies virus, that’s the technology what we are dealing today. MR. HIMANSHU DIWAKAR JETGI 3

4. Basics of Very Large Scale Integration (VLSI) CMOS Digital Integrated circuits – Analysis and Design by Sung – Mo Kang, Yusuf Leblebici , TATA McGraw-Hill Pub. Company Ltd. MR. HIMANSHU DIWAKAR JETGI 4

5. Brief History and Introduction MR. HIMANSHU DIWAKAR JETGI 5 Fig.1.1.Invention of transistor by John Bardeen, William shockely and Walter (1947) at Bell Lab 23 rd Dec

6. Introduction… MICROPROCESSORS are essential to many of products we use every day such as TVs, cars, radios , home appliances and of course computers. Transistors are the main components of microprocessors. At their most basic level, transistors may seem simple. But their development actually requires many years of painstaking research. Before processors transistors computers relied on slow, inefficient vacuum tubes and mechanical switches to process information. In 1958, engineers managed to put two transistors onto a single crystal and create the first integrated circuit, which subsequently led to the first microprocessors . MR. HIMANSHU DIWAKAR JETGI 6

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8. Moore's law " Moore's law " is the observation that, over the history of computing hardware, the number of transistors in a dense integrated circuit has doubled approximately every two years . MR. HIMANSHU DIWAKAR JETGI 8

9. Evolution of logic complexity in integrated circuit Era Date Complexity Single transistor 1958 <1 Unit logic (one gate) 1960 1 Multifunction 1962 2-4 Complex function (SSI) 1964 5-20 Medium scale integration (MSI) 1967 20-200 Large scale integration (LSI) 1972 200-2,000 Very large scale integration (VLSI) 1978 2,000-20,000 Ultra large scale integration (ULSI) 1989 >20,000 MR. HIMANSHU DIWAKAR JETGI 9

10. Limitations of Moore's law MR. HIMANSHU DIWAKAR JETGI 10 Growth expect until 30nm gate length (currently: 45nm) 3D shift design needed in fabrication process 3D shift design in VLSI

11. Cont’d Higher the growth in VLSI technology needs some structured design methodology for economically viable VLSI products, in timely manner . Logic chips (microprocessors) have more complex design compare to memory chips. The complexity is also increased exponentially for logic chips. This increase in design cycle time of chips. This time is strongly dependent on the efficiency of the design methodologies as well as on design style. As shown in upcoming figure, two different design styles are compared for their relative merits and demerits . MR. HIMANSHU DIWAKAR JETGI 11

12. Cont’d Full custom design style (where the geometry and the placement of every transistor can be optimized individually) requires a longer time until design maturity can be reached. But the final product have the higher level of performance . In semicustom design style (standard cell based or FPGA) will allow a shorter design time until design maturity can be achieved. The choice is of design style depends on performance requirements of the VLSI product . MR. HIMANSHU DIWAKAR JETGI 12

13. Overview of VLSI design methodology MR. HIMANSHU DIWAKAR JETGI 13

14. Approximately every two years, a new generation of Technology is introduced . This may require that the level of logic integration and chip performance fall short of the level achievable with the current processing technology.(see upcoming figure) It can be seen that the design cycle time of a successful VLSI product is kept shorter than what would be necessary for developing an optimum performance. The use of CAD tools methodologies are also essential for reducing the design cycle time for managing the increasing design complexity . MR. HIMANSHU DIWAKAR JETGI 14

15. VLSI design flow The Y-chart (first introduced by D. Gajski ) shown in Fig. 1.4 illustrates a design flow for most logic chips, using design activities on three different axes (domains) which resemble the letter Y. The Y-chart consists of three major domains, namely: behavioral domain, structural domain, geometrical layout domain . MR. HIMANSHU DIWAKAR JETGI 15

16. VLSI design flow MR. HIMANSHU DIWAKAR JETGI 16 Figure-1.4:  Typical VLSI design flow in three domains (Y-chart representation).

17. VLSI design flow The design flow starts from the algorithm that describes the behavior of the target chip . The corresponding architecture of the processor is first defined. It is mapped onto the chip surface by floor planning. The next design evolution in the behavioral domain defines finite state machines (FSMs) which are structurally implemented with functional modules such as registers and arithmetic logic units (ALUs). These modules are then geometrically placed onto the chip surface using CAD tools for automatic module placement followed by routing, with a goal of minimizing the interconnects area and signal delays . MR. HIMANSHU DIWAKAR JETGI 17

18. VLSI design flow Figure-5 provides a more simplified view of the VLSI design flow, taking into account the various representations, or abstractions of design - behavioral, logic, circuit and mask layout.  Note that the verification of design plays a very important role in every step during this process. The failure to properly verify a design in its early phases typically causes significant and expensive re-design at a later stage, which ultimately increases the time-to-market . MR. HIMANSHU DIWAKAR JETGI 18

19. VLSI design flow Figure-5 :  A more simplified view of VLSI design flow. MR. HIMANSHU DIWAKAR JETGI 19 Functional verification System specifications Functional (Architecture) Design Logic design Logic verification Circuit Design Circuit verification Physical Design Layout verification Fabrication and testing Behavioral Representation Behavioral (Gate level) Representation Circuit Representation Layout Representation VLSI Design Flow

20. VLSI design flow Although the design process has been described in linear fashion for simplicity, in reality there are many iterations back and forth, especially between any two neighboring steps, and occasionally even remotely separated pairs . In the following, we will examine design methodologies and structured approaches which have been developed over the years to deal with both complex hardware and software projects.  Some of the classical techniques for reducing the complexity of IC design are: Hierarchy, regularity, modularity and locality . MR. HIMANSHU DIWAKAR JETGI 20

21. Concept of regularity, Modularity, and Locality The hierarchical design approach reduces the design complexity by dividing the large system into several sub-modules . Regularity means that the hierarchical decomposition of a large system should result in not only simple, but also similar blocks, as much as possible. A good example of regularity is the design of array structures consisting of identical cells - such as a parallel multiplication array.  Regularity can exist at all levels of abstraction: At the transistor level, uniformly sized transistors simplify the design. At the logic level, identical gate structures can be used etc . MR. HIMANSHU DIWAKAR JETGI 21

22. Concept of regularity, Modularity, and Locality Figure 1.11 shows regular circuit-level designs of a 2-1 MUX (multiplexer), an D-type edge-triggered flip flop, and a one-bit full adder . Note that all of these circuits were designed by using inverters and tri-state buffers only. If the designer has a small library of well-defined and well-characterized basic building blocks, a number of different functions can be constructed by using this principle .   Regularity usually reduces the number of different modules that need to be designed and verified, at all levels of abstraction. MR. HIMANSHU DIWAKAR JETGI 22

23. Regularity Figure 1.11 shows regular circuit-level designs of a 2-1 MUX (multiplexer), an D-type edge-triggered flip flop, and a one-bit full adder . Note that all of these circuits were designed by using inverters and tri-state buffers only. If the designer has a small library of well-defined and well-characterized basic building blocks, a number of different functions can be constructed by using this principle.  Regularity usually reduces the number of different modules that need to be designed and verified, at all levels of abstraction. MR. HIMANSHU DIWAKAR JETGI 23

24. Regularity MR. HIMANSHU DIWAKAR JETGI 24 Figure-1.11:  Regular design of a 2-1 MUX, a DFF and an adder, using inverters and tri-state buffers.

25. Modularity Modularity in design means that the various functional blocks which make up the larger system must have well-defined functions and interfaces.  Modularity allows that each block or module can be designed relatively independently from each other, since there is no ambiguity about the function and the signal interface of these blocks. All of the blocks can be combined with ease at the end of the design process, to form the large system . MR. HIMANSHU DIWAKAR JETGI 25

26. Locality The concept of modularity enables the parallelization of the design process. It also allows the use of generic modules in various designs - the well-defined functionality and signal interface allow plug-and-play design . By defining well-characterized interfaces for each module in the system, we effectively ensure that the internals of each module become unimportant to the exterior modules. Internal details remain at the local level. The concept of locality also ensures that connections are mostly between neighboring modules, avoiding long-distance connections as much as possible . MR. HIMANSHU DIWAKAR JETGI 26

27. Locality  This last point is extremely important for avoiding excessive interconnect delays. Time-critical operations should be performed locally, without the need to access distant modules or signals. If necessary, the replication of some logic may solve this problem in large system architectures. MR. HIMANSHU DIWAKAR JETGI 27

28. Thank you MR. HIMANSHU DIWAKAR JETGI 28