Vlsi design flow

VLSI DESIGN FLOW

1. FLOW CHART FOR VLSI DESIGN FLOW d ESIGN SPECIFICATION DESIGN ENTRY FUNCTIONAL SIMULATION PLANNING PLACEMENT AND ROUTING(PPR) TIMING SIMULATION FUSING/FABRICATION IN TO THE CHIP VLSI DESIGN FLOW

2. FLOW CHART FOR VLSI DESIGN FLOW

3. DESIGN SPECIFICATION The Algorithm to be implemented in detail with mathematical representation. Number of inputs and outputs in the design and number of bits in each of them. Number of bits used in the internal arithmetic operation. Number of clock signals to be used in the design. Maximum clock frequency to be used. Area of the chip. Power dissipation in the chip.

4. DESIGN ENTRY TWOTYPES Schematic Entry Hardware Description Language Verilog HDL. VHDL.

5. DESIGN ENTRY

6. FUNCTIONAL SIMULATION Before Design implementation , functional simulation is performed to verify the logic created is correct or not. Design methodology determines it performance. Schematic Flow-It is performed directly after completing design within the design entry tools. HDL Flow-It is performed after the design has been entered and synthesized.

7. FUNCTIONAL SIMULATION OF T- FLIPFLOP

8. PLANNING PLACEMENT AND ROUTING(PPR) VLSI physical design or Layout phase Automated design process using Computer Aided Design(CAD) Tools. Various phases Partitioning Floor planning Placement Routing

9. PLANNING PLACEMENT AND ROUTING(PPR) PARTITIONING:- Task of dividing a circuit in such a way so that the area of each sub-circuit is well with in the prescribed range and number of interconnection between sub-circuits is also minimized. FLOOR PLANNING:- Step to determine the shape of each sub circuit module and pin location at their boundary and find out the approximate location of each module in a rectangular chip.

10. PLANNING PLACEMENT AND ROUTING(PPR) PLACEMENT:- It is the problem of determination of best position of each module, when each module has a fixed shape , area and terminals . ROUTING:- It is the method of interconnection of different circuit components, with an aim to minimize the chip area and also reduction of total wire-length. Two types Global Routing Channel Routing

11. PARTITIONING & FLOORPLANNING

12. PLACEMENT & ROUTING

13. TIMING SIMULATION Constitutes on NET Delays and GATE Delays. Delays encountered by a signal for traversing from output of one gate to the input of another gate is called NET Delays. Delays from input of one gate to the output of same gate due to propagation time of the gate is called GATE Delays. It is done with the clock speed.

14. FUSING/FABRICATION IN TO THE CHIP Last step in VLSI Design. Two different design styles Full custom Semi custom Cell based design Array based design

15. FUSING/FABRICATION IN TO THE CHIP FULL CUSTOM:- The semiconductor chips are ASIC’s which are designed specifically for a given application or application domain. SEMI-CUSTOM:- CELL BASED DESIGN – uses libraries of predesigned cells which are then placed and wired to complete the design. ARRAY BASED DESIGN – uses a prefabricated matrix of non-connected components. FPGA uses programmable logic modules and also programmable interconnections in which configuration data is loaded during each application.