VLSI for Low Power design and circuit.ppt

A unit of the low power VLSI design. It provides a brief description of the techniques and how to reduce the power consumption in a Very large scale integrated device. Along with the reason why the low power has come into picture.

1. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 11
ELEC 5770-001/6770-001 Fall 2010
VLSI Design
Low Power VLSI Design
Vishwani D. AgrawalVishwani D. Agrawal
James J. Danaher ProfessorJames J. Danaher Professor
Dept. of Electrical and Computer EngineeringDept. of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849Auburn University, Auburn, AL 36849
[email protected]
http://www.eng.auburn.edu/~
vagrawal/COURSE/E6770_Fall10/VLSID_Fall2010_LowPower.ppt

2. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 22
Power Consumption of VLSI Chips
Why is it a concern?

3. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 33
ISSCC, Feb. 2001, Keynote
“Ten years from now,
microprocessors will run at
10GHz to 30GHz and be capable
of processing 1 trillion operations
per second – about the same
number of calculations that the
world's fastest supercomputer
can perform now.
“Unfortunately, if nothing
changes these chips will produce
as much heat, for their
proportional size, as a nuclear
reactor. . . .”
Patrick P. Gelsinger
Senior Vice President
General Manager
Digital Enterprise Group
INTEL CORP.

4. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 44
VLSI Chip Power Density
4004
8008
8080
8085
8086
286
386
486
Pentium®
P6
1
10
100
1000
10000
1970 1980 1990 2000 2010
Year
P
o
w
e
r

D
e
n
s
i
t
y

(
W
/
c
m
2
)
Hot Plate
Nuclear
Reacto
r
Rocket
Nozzle
Sun’s
Surface
Source: Intel

5. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 55
Low-Power Design

Design practices that reduce power Design practices that reduce power
consumption at least by one order of consumption at least by one order of
magnitude; in practice 50% reduction is magnitude; in practice 50% reduction is
often acceptable.often acceptable.

Low-power design methods:Low-power design methods:

Algorithms and architecturesAlgorithms and architectures

High-level and software techniquesHigh-level and software techniques

Gate and circuit-level methodsGate and circuit-level methods

Test powerTest power

6. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 66
Specific Topics in Low-Power

Power dissipation in CMOS circuitsPower dissipation in CMOS circuits

Transistor-level methodsTransistor-level methods

Low-power CMOS technologiesLow-power CMOS technologies

Energy recovery methodsEnergy recovery methods

Ultra low power logic (subthreshold VDD)Ultra low power logic (subthreshold VDD)

Circuit and gate level methodsCircuit and gate level methods

Logic synthesisLogic synthesis

Dynamic power reduction techniquesDynamic power reduction techniques

Leakage power reductionLeakage power reduction

System level methodsSystem level methods

MicroprocessorsMicroprocessors

Arithmetic circuitsArithmetic circuits

Low power memory technologyLow power memory technology

Test PowerTest Power

Power estimationPower estimation

7. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 77
CMOS Logic (Inverter)
F. M. Wanlass and C. T. Sah, “Nanowatt Logic using Field-
Effect Metal-Oxide-Semiconductor Triodes,” IEEE International
Solid-State Circuits Conference Digest, vol. IV, February 1963,
pp. 32-33.
No current flows
from power supply!
Where is power
consumed?
VDD
GND

8. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 88
Components of Power

Dynamic, when output changesDynamic, when output changes

Signal transitions (major component)Signal transitions (major component)

Logic activityLogic activity

GlitchesGlitches

Short-circuit (small)Short-circuit (small)

Static, when signal is in steady stateStatic, when signal is in steady state

Leakage (used to be small)Leakage (used to be small)
P
total =P
dyn + P
stat
=P
tran
+ P
sc + P
stat

9. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 99
Power of a Transition: P
tran
VV
GroundGround
C
R = R
on
Large
resistance
v
i
(t) v(t)
i(t)
C

=Total load capacitance for gate; includes transistor capacitances
of driving gate + routing capacitance + transistor capacitances
of driven gates; obtained by layout analysis.

10. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 1010
Charging of a Capacitor
V
C
R
i(t)
v(t)
Charge on capacitor, q(t) =C v(t)
Current, i(t)=dq(t)/dt=C dv(t)/dt
t = 0

11. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 1111
i(t)=C dv(t)/dt=[V – v(t)] /R
dv(t) dt
∫ ───── =∫ ────

V – v(t) RC
– t
ln [V – v(t)]=──+ A
RC
Initial condition, t = 0, v(t) = 0 → A = ln V
– t
v(t) =V [1 – exp(───)]
RC

12. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 1212
– t
v(t)=V [1 – exp( ── )]
RC
dv(t) V – t
i(t)=C ───=── exp( ── )
dt R RC

13. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 1313
Total Energy Per Charging
Transition from Power Supply
∞ ∞ V
2
– t
E
trans=∫ V i(t) dt=∫ ── exp( ── ) dt
0 0 R RC
=CV
2

14. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 1414
Energy Dissipated Per Transition in
Resistance
∞ V
2
∞ – 2t
R ∫ i
2
(t) dt =R ── ∫ exp( ── ) dt
0 R
2
0 RC
1
=─ CV
2
2

15. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 1515
Energy Stored in Charged Capacitor
∞ ∞ – t V – t
∫ v(t) i(t) dt = ∫ V [1 – exp( ── )] ─ exp( ── ) dt
0 0 RC R RC
1
= ─ CV
2
2

16. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 1616
Transition Power

Gate output rising transitionGate output rising transition

Energy dissipated in pMOS transistor = Energy dissipated in pMOS transistor = CV CV
22
/2/2

Energy stored in capacitor = Energy stored in capacitor = CV CV
22
/2/2

Gate output falling transitionGate output falling transition

Energy dissipated in nMOS transistor = Energy dissipated in nMOS transistor = CV CV
22
/2/2

Energy dissipated per transition = Energy dissipated per transition = CV CV
22
/2/2

Power dissipation:Power dissipation:
P
trans=E
trans α f
ck=α f
ck CV
2
/2
α=activity factor
f
ck = clock frequency

17. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 1717
Components of Power

DynamicDynamic

Signal transitionsSignal transitions

Logic activityLogic activity

GlitchesGlitches

Short-circuitShort-circuit

StaticStatic

LeakageLeakage
P
total =P
dyn + P
stat
=P
tran + P
sc + P
stat

18. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 1818
Short Circuit Power of a Transition: P
sc
VV
DDDD
GroundGround
C
L
v
i
(t) v
o
(t)
i
sc
(t)

19. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 1919
Short-Circuit Power

Increases with rise and fall times of input.Increases with rise and fall times of input.

Decreases for larger output load Decreases for larger output load
capacitance; large capacitor takes most of capacitance; large capacitor takes most of
the current.the current.

Small, about 5-10% of dynamic power Small, about 5-10% of dynamic power
dissipated in charging and discharging of dissipated in charging and discharging of
the output capacitance.the output capacitance.
Becomes zero when Becomes zero when VV
DDDD ≤ V ≤ V
thnthn + + VV
thpthp

20. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 2020
Components of Power

DynamicDynamic

Signal transitionsSignal transitions

Logic activityLogic activity

GlitchesGlitches

Short-circuitShort-circuit

StaticStatic

LeakageLeakage

21. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 2121
Static (Leakage) Power

Leakage power as a fraction of the total power Leakage power as a fraction of the total power
increases as clock frequency drops. increases as clock frequency drops. Turning Turning
supply off in unused parts can save powersupply off in unused parts can save power..

For a gate it is a small fraction of the total power; For a gate it is a small fraction of the total power;
it can be significant for very large circuits.it can be significant for very large circuits.
Static power increases as feature size is scaled Static power increases as feature size is scaled
down; controlling leakage is an important aspect down; controlling leakage is an important aspect
of transistor design and semiconductor process of transistor design and semiconductor process
technology.technology.

22. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 2222
CMOS Gate Power
VV
GroundGround
C
R = R
on
Large
resistance
v
i
(t) v(t)
i(t)
time
v
i
(t)
i(t)
i
sc
(t)
Leakage
current

23. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 2323
Some Examples

24. Energy Saving by Voltage Reduction
Battery
size
VDD = 0.9V, 500MHz VDD = 0.3V, 5MHz
Efficiency
%
Battery lifetime
Efficiency
%
Battery lifetime
AHr
x10
3

seconds
x10
11

cycles
x10
3

seconds
x10
11

cycles
1.2 93 1.2637.03100+ 123448.60
3.6 103 4.19822.80100+ 3894150.30
Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 2424
seven-times
70 million gate circuit, 45nm CMOS bulk PTM.
Lithium-ion battery.
Ref.: M. Kulkarni and V. D. Agrawal, “A Tutorial on Battery
Simulation – Matching Power Source to Electronic
System,” Proc. VLSI Design and Test Symp., July 2010.

25. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 2525
State Encoding for a Counter
Two-bit binary counter:Two-bit binary counter:

State sequence, 00 → 01 → 10 → 11 → 00State sequence, 00 → 01 → 10 → 11 → 00

Six bit transitions in four clock cyclesSix bit transitions in four clock cycles
6/4 = 1.5 transitions per clock6/4 = 1.5 transitions per clock
Two-bit Gray-code counterTwo-bit Gray-code counter

State sequence, 00 → 01 → 11 → 10 → 00State sequence, 00 → 01 → 11 → 10 → 00

Four bit transitions in four clock cyclesFour bit transitions in four clock cycles
4/4 = 1.0 transition per clock4/4 = 1.0 transition per clock

Gray-code counter is more power efficient.Gray-code counter is more power efficient.
G. K. Yeap, Practical Low Power Digital VLSI Design, Boston:
Kluwer Academic Publishers (now Springer), 1998.

26. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 2626
Binary Counter: Original Encoding
Present Present
statestate
Next stateNext state
aa bb AA BB
00 00 00 11
00 11 11 00
11 00 11 11
11 11 00 00
A
B
a
b
CK
CLR
babaB
babaA



27. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 2727
Binary Counter: Gray Encoding
Present Present
statestate
Next stateNext state
aa bb AA BB
00 00 00 11
00 11 11 11
11 00 00 00
11 11 11 00
A
B
a
b
CK
CLR
babaB
abbaA



28. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 2828
Three-Bit Counters
BinaryBinary Gray-codeGray-code
StateState No. of togglesNo. of togglesStateState No. of togglesNo. of toggles
000000 -- 000000 --
001001 11 001001 11
010010 22 011011 11
011011 11 010010 11
100100 33 110110 11
101101 11 111111 11
110110 22 101101 11
111111 11 100100 11
000000 33 000000 11
Av. Transitions/clock = 1.75Av. Transitions/clock = 1.75 Av. Transitions/clock = 1Av. Transitions/clock = 1

29. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 2929
N-Bit Counter: Toggles in Counting Cycle

Binary counter: T(binary) = 2(2Binary counter: T(binary) = 2(2
NN
– 1) – 1)

Gray-code counter: T(gray) = 2Gray-code counter: T(gray) = 2
NN

T(gray)/T(binary) = 2T(gray)/T(binary) = 2
N-1N-1
/(2/(2
NN
– 1) → 0.5 – 1) → 0.5
BitsBits T(binary)T(binary) T(gray)T(gray) T(gray)/T(binary)T(gray)/T(binary)
11 22 22 1.01.0
22 66 44 0.66670.6667
33 1414 88 0.57140.5714
44 3030 1616 0.53330.5333
55 6262 3232 0.51610.5161
66 126126 6464 0.50790.5079
∞∞ -- -- 0.50000.5000

30. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 3030
FSM State Encoding
11
0100
0.1
0.1
0.4
0.3
0.6
0.9
0.6
01
1100
0.1
0.1
0.4
0.3
0.6
0.9
0.6
Expected number of state-bit transitions:
1(0.3+0.4+0.1) + 2(0.1) = 1.0
Transition
probability
based on
PI statistics
State encoding can be selected using a power-based cost function.
2(0.3+0.4) + 1(0.1+0.1) = 1.6

31. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 3131
FSM: Clock-Gating
Moore machine: Outputs depend only on Moore machine: Outputs depend only on
the state variables.the state variables.

If a state has a self-loop in the state transition If a state has a self-loop in the state transition
graph (STG), then clock can be stopped graph (STG), then clock can be stopped
whenever a self-loop is to be executed.whenever a self-loop is to be executed.
Sj
Si
Sk
Xi/Zk
Xk/Zk
Xj/Zk
Clock can be stopped
when (Xk, Sk) combination
occurs.

32. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 3232
Clock-Gating in Moore FSM
Combinational
logic
Latch
Clock
activation
logic
F
lip
-
f
lo
p
s
PI
CK
PO
L. Benini and G. De Micheli,
Dynamic Power Management,
Boston: Springer, 1998.

33. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 3333
Bus Encoding for Reduced Power

Example: Four bit busExample: Four bit bus
0000 → 1110 has three transitions.0000 → 1110 has three transitions.
If bits of second pattern are inverted, then 0000 → If bits of second pattern are inverted, then 0000 →
0001 will have only one transition.0001 will have only one transition.
Bit-inversion encoding for N-bit bus:Bit-inversion encoding for N-bit bus:
Number of bit transitions
0 N/2 N
N
N/2
0
N
u
m
b
e
r

o
f

b
it

t
r
a
n
s
it
io
n
s

a
f
t
e
r

in
v
e
r
s
io
n

e
n
c
o
d
in
g

34. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 3434
Bus-Inversion Encoding Logic
Polarity
decision
logic
S
e
n
t

d
a
t
a
R
e
c
e
iv
e
d

d
a
t
a
Bus register
Polarity bit
M. Stan and W. Burleson, “Bus-
Invert Coding for Low Power I/O,”
IEEE Trans. VLSI Systems, vol. 3, no.
1, pp. 49-58, March 1995.

35. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 3535
Clock-Gating in Low-Power Flip-Flop
D Q
D
CK

36. S5378 with Gated-Clock FF

2958 gates, 179 flip-flops2958 gates, 179 flip-flops

TSMC025 CMOSTSMC025 CMOS

1,000 random vectors, clock period 50ns1,000 random vectors, clock period 50ns

Simulation by Powersim*Simulation by Powersim*
Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 3636
Flip-
flops
used
Power (microwatts)
Combinational logic
ClockFlip-flopsTotal
Transitions
Short-
circuit
Static
(leakage)
Normal 95.4 14.1 0.13 220.3 751.61,081.5
Gated 133.5 23.1 0.13 118.9 32.5 308.0
J. D. Alexander, “Simulation Based Power Estimation for Digital CMOS
Technologies,” Master’s Thesis, Auburn University, Dec. 2008.
*

37. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 3737
Books on Low-Power Design (1)

L. Benini and G. De Micheli, L. Benini and G. De Micheli, Dynamic Power Management Design Techniques and Dynamic Power Management Design Techniques and
CAD ToolsCAD Tools, Boston: Springer, 1998., Boston: Springer, 1998.

T. D. Burd and R. A. Brodersen, T. D. Burd and R. A. Brodersen, Energy Efficient Microprocessor DesignEnergy Efficient Microprocessor Design, Boston: , Boston:
Springer, 2002.Springer, 2002.

A. Chandrakasan and R. Brodersen, A. Chandrakasan and R. Brodersen, Low-Power Digital CMOS DesignLow-Power Digital CMOS Design, Boston: , Boston:
Springer, 1995.Springer, 1995.

A. Chandrakasan and R. Brodersen, A. Chandrakasan and R. Brodersen, Low-Power CMOS DesignLow-Power CMOS Design, New York: IEEE , New York: IEEE
Press, 1998.Press, 1998.

J.-M. Chang and M. Pedram, J.-M. Chang and M. Pedram, Power Optimization and Synthesis at Behavioral and Power Optimization and Synthesis at Behavioral and
System Levels using Formal MethodsSystem Levels using Formal Methods, Boston: Springer, 1999., Boston: Springer, 1999.

M. S. Elrabaa, I. S. Abu-Khater and M. I. Elmasry, M. S. Elrabaa, I. S. Abu-Khater and M. I. Elmasry, Advanced Low-Power Digital Advanced Low-Power Digital
Circuit TechniquesCircuit Techniques, Boston: Springer, 1997., Boston: Springer, 1997.

R. Graybill and R. Melhem, R. Graybill and R. Melhem, Power Aware ComputingPower Aware Computing, New York: Plenum Publishers, , New York: Plenum Publishers,
2002.2002.

S. Iman and M. Pedram, S. Iman and M. Pedram, Logic Synthesis for Low Power VLSI DesignsLogic Synthesis for Low Power VLSI Designs, Boston: , Boston:
Springer, 1998.Springer, 1998.

J. B. Kuo and J.-H. Lou, J. B. Kuo and J.-H. Lou, Low-Voltage CMOS VLSI CircuitsLow-Voltage CMOS VLSI Circuits, New York: Wiley-, New York: Wiley-
Interscience, 1999.Interscience, 1999.

J. Monteiro and S. Devadas, J. Monteiro and S. Devadas, Computer-Aided Design Techniques for Low Power Computer-Aided Design Techniques for Low Power
Sequential Logic CircuitsSequential Logic Circuits, Boston: Springer, 1997., Boston: Springer, 1997.

S. G. Narendra and A. Chandrakasan, S. G. Narendra and A. Chandrakasan, Leakage in Nanometer CMOS TechnologiesLeakage in Nanometer CMOS Technologies, ,
Boston: Springer, 2005.Boston: Springer, 2005.

W. Nebel and J. Mermet, W. Nebel and J. Mermet, Low Power Design in Deep Submicron ElectronicsLow Power Design in Deep Submicron Electronics, Boston: , Boston:
Springer, 1997.Springer, 1997.

38. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 3838
Books on Low-Power Design (2)

N. Nicolici and B. M. Al-Hashimi, N. Nicolici and B. M. Al-Hashimi, Power-Constrained Testing of VLSI CircuitsPower-Constrained Testing of VLSI Circuits, ,
Boston: Springer, 2003.Boston: Springer, 2003.

V. G. Oklobdzija, V. M. Stojanovic, D. M. Markovic and N. Nedovic, V. G. Oklobdzija, V. M. Stojanovic, D. M. Markovic and N. Nedovic, Digital System Digital System
Clocking: High Performance and Low-Power AspectsClocking: High Performance and Low-Power Aspects, Wiley-IEEE, 2005., Wiley-IEEE, 2005.

M. Pedram and J. M. Rabaey, M. Pedram and J. M. Rabaey, Power Aware Design MethodologiesPower Aware Design Methodologies, Boston: , Boston:
Springer, 2002.Springer, 2002.

C. Piguet, C. Piguet, Low-Power Electronics DesignLow-Power Electronics Design, Boca Raton: Florida: CRC Press, 2005., Boca Raton: Florida: CRC Press, 2005.

J. M. Rabaey and M. Pedram, J. M. Rabaey and M. Pedram, Low Power Design MethodologiesLow Power Design Methodologies, Boston: , Boston:
Springer, 1996.Springer, 1996.

S. Roudy, P. K. Wright and J. M. Rabaey, S. Roudy, P. K. Wright and J. M. Rabaey, Energy Scavenging for Wireless Sensor Energy Scavenging for Wireless Sensor
NetworksNetworks, Boston: Springer, 2003., Boston: Springer, 2003.

K. Roy and S. C. Prasad, K. Roy and S. C. Prasad, Low-Power CMOS VLSI Circuit DesignLow-Power CMOS VLSI Circuit Design, New York: Wiley-, New York: Wiley-
Interscience, 2000.Interscience, 2000.

E. Sánchez-Sinencio and A. G. Andreaou, E. Sánchez-Sinencio and A. G. Andreaou, Low-Voltage/Low-Power Integrated Low-Voltage/Low-Power Integrated
Circuits and Systems – Low-Voltage Mixed-Signal CircuitsCircuits and Systems – Low-Voltage Mixed-Signal Circuits, New York: IEEE , New York: IEEE
Press, 1999.Press, 1999.

W. A. Serdijn, W. A. Serdijn, Low-Voltage Low-Power Analog Integrated CircuitsLow-Voltage Low-Power Analog Integrated Circuits, ,
Boston:Springer, 1995.Boston:Springer, 1995.

S. Sheng and R. W. Brodersen, S. Sheng and R. W. Brodersen, Low-Power Wireless Communications: A Low-Power Wireless Communications: A
Wideband CDMA System DesignWideband CDMA System Design , Boston: Springer, 1998., Boston: Springer, 1998.

G. Verghese and J. M. Rabaey, G. Verghese and J. M. Rabaey, Low-Energy FPGAsLow-Energy FPGAs, Boston: springer, 2001., Boston: springer, 2001.

G. K. Yeap, G. K. Yeap, Practical Low Power Digital VLSI DesignPractical Low Power Digital VLSI Design, Boston:Springer, 1998., Boston:Springer, 1998.

K.-S. Yeo and K. Roy, K.-S. Yeo and K. Roy, Low-Voltage Low-Power SubsystemsLow-Voltage Low-Power Subsystems, McGraw Hill, 2004., McGraw Hill, 2004.

39. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 3939
Books Useful in Low-Power Design

A. Chandrakasan, W. J. Bowhill and F. Fox, A. Chandrakasan, W. J. Bowhill and F. Fox, Design of High-Design of High-
Performance Microprocessor Circuits, Performance Microprocessor Circuits, New York: IEEE Press, New York: IEEE Press,
2001.2001.

R. C. Jaeger and T. N. Blalock, R. C. Jaeger and T. N. Blalock, Microelectronic Circuit Design, Microelectronic Circuit Design,
Third EditionThird Edition, McGraw-Hill, 2006., McGraw-Hill, 2006.

S. M. Kang and Y. Leblebici, S. M. Kang and Y. Leblebici, CMOS Digital Integrated CircuitsCMOS Digital Integrated Circuits, ,
New York: McGraw-Hill, 1996.New York: McGraw-Hill, 1996.

E. Larsson, E. Larsson, Introduction to Advanced System-on-Chip Test Introduction to Advanced System-on-Chip Test
Design and OptimizationDesign and Optimization, Springer, 2005., Springer, 2005.

J. M. Rabaey, A. Chandrakasan and B. Nikolić, J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Digital Integrated
Circuits, Second EditionCircuits, Second Edition, Upper Saddle River, New Jersey: , Upper Saddle River, New Jersey:
Prentice-Hall, 2003.Prentice-Hall, 2003.

J. Segura and C. F. Hawkins, J. Segura and C. F. Hawkins, CMOS Electronics, How It Works, CMOS Electronics, How It Works,
How It FailsHow It Fails, New York: IEEE Press, 2004., New York: IEEE Press, 2004.

N. H. E. Weste and D. Harris, N. H. E. Weste and D. Harris, CMOS VLSI Design, Third EditionCMOS VLSI Design, Third Edition, ,
Reading, Massachusetts: Addison-Wesley, 2005.Reading, Massachusetts: Addison-Wesley, 2005.

40. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 4040
Problem: Bus Encoding
A 1-hot encoding is to be used for reducing the capacitive
power consumption of an n-bit data bus. All n bits are assumed
to be independent and random. Derive a formula for the ratio
of power consumptions on the encoded and the un-coded
buses. Show that n 4 is essential for the 1-hot encoding to be
≥
beneficial.
Reference: A. P. Chandrakasan and R. W. Brodersen, Low Power
Digital CMOS Design, Boston: Kluwer Academic Publishers, 1995,
pp. 224-225. [Hint: You should be able to solve this problem
without the help of the reference.]

41. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 4141
Solution: Bus Encoding
Un-coded bus: Two consecutive bits on a wire can be 00, 01, 10 and
11, each with a probability 0.25. Considering only the 01
transition, which draws energy from the supply, the probability of
a data pattern consuming CV
2
energy on a wire is ¼. Therefore,
the average per pattern energy for all n wires of the bus is CV
2
n/4.
Encoded bus: Encoded bus contains 2
n
wires. The 1-hot encoding
ensures that whenever there is a change in the data pattern,
exactly one wire will have a 01 transition, charging its capacitance
and consuming CV
2
energy. There can be 2
n
possible data
patterns and exactly one of these will match the previous pattern
and consume no energy. Thus, the per pattern energy
consumption of the bus is 0 with probability 2
–n
, and CV
2
with
probability 1 – 2
–n
. The average per pattern energy for the 1-hot
encoded bus is CV
2
(1 – 2
–n
).

42. Fall 2010, Nov 16Fall 2010, Nov 16 ELEC5770-001/6770-001 Guest LectureELEC5770-001/6770-001 Guest Lecture 4242
Solution: Bus Encoding (Cont.)
Power ratio = Encoded bus power / un-coded bus power
= 4(1 – 2
–n
)/n 4/
→
n for large n
For the encoding to be beneficial, the above power ratio should
be less than 1. That is, 4(1 – 2
–n
)/n 1, or 1 – 2
≤
–n

≤
n/4, or n/4 1
≥
(approximately)
→
n 4.
≥
The following table shows 1-hot encoded bus power ratio as a
function of bus width:
n 4(1 – 2
–n
)/n n 4(1 – 2
–n
)/n
1 2.0000 8 0.4981
2 1.5000 16 0.2500 = 1/4
3 1.1670 32 1/8
4 0.9375 64 1/16