Washing Machine Controller project ppt on VLSI

The components and code and schematic of th washin machine controller

1. Washing Machine Controller
using SystemVerilog
•FSM-based Sequential System Design
•Presented by:
•Sandeep Marode
•www.linkedin.com/in/sandeep-marode
•https://chat.whatsapp.com/KpyWN5f1MBLIrPzEgjZ
DdP

2. Introduction & Motivation
•Objective: Design a controller that automates
the operation of a washing machine.
•Real-world importance: Used in almost every
household and commercial laundry system.
•Relevance: Applies complex FSM logic, timer
integration, and sequential modeling in RTL
design.

3. Need for Washing Machine
Controller
•- Automates complete washing process.
•- Improves energy and water efficiency.
•- Eliminates human error.
•- Enables smart features and safety interlocks.

4. Requirement Gathering
•Inputs:
•- clk, rst, start (user input)
•- water_level_full, drain_empty (sensor input)
•Outputs:
•- fill_valve_on, drain_valve_on
•- motor_cw, motor_ccw, motor_off
•Parameters:
•- FILL_TIME, WASH_TIME, DRAIN_TIME, RINSE_TIME,
SPIN_TIME

5. Challenges in Controller Design
•- Timing-sensitive operations for each cycle.
•- Sensor signal reliability.
•- Sequential transitions and interlocks.
•- Reset and start/restart conditions.
•- Synchronizing multiple operations: fill, drain,
motor.

6. Assumptions
•- Sensor signals are glitch-free and debounced.
•- Only one cycle executes at a time.
•- Start signal is high for one cycle.
•- Motor only rotates clockwise for simplicity.

7. Constraints
•- No user input during mid-cycle.
•- Finite memory and resource constraints.
•- Counter-based timer instead of real-time
clock.
•- Simplified water level detection (binary).

8. Applications
•- Domestic and commercial washing machines
•- Embedded appliance controllers
•- Training projects in RTL design courses
•- Smart home appliances with automation

9. Block Diagram
•Components:
•- Sensor Interface
•- FSM Controller
•- Timer Block
•- Output Control Logic
•- User Control Interface

10. FSM Overview
•States:
•1. IDLE
•2. FILL
•3. WASH
•4. DRAIN
•5. RINSE
•6. SPIN
•7. END
•Transition based on: start, sensor values, and internal
timers.

11. FSM State Diagram
•[Insert Visual FSM Diagram with Arrows and
State Names]

12. Timer Logic Design
•Counter increments in WASH, RINSE, SPIN states.
•Resets on state transition.
•Uses parameter values for cycle duration.
•Verilog snippet:
•if (state == WASH || state == RINSE || state ==
SPIN)
• timer <= timer + 1;
•else
• timer <= 0;

13. Output Control Mapping
STATES fill_valvedrain_valvemotor_cw motor_off
IDLE 0 0 0 1
FILL 1 0 0 0
WASH 0 0 1 0
DRAIN 0 1 0 0
RINSE 1 0 1 0
SPIN 0 1 1 0
END 0 0 0 1

14. Testbench Scenarios
•- Start wash cycle, monitor transitions
•- Vary sensor input delays
•- Restart after END
•- Reset during WASH

15. Conclusion
•- Demonstrates real-world FSM control.
•- Trains timer and sequential logic integration.
•- Builds habit of modular design.
•- Foundation for appliance automation
systems.

16. Q&A / Discussion
•- Discuss possible extensions:
• - Bi-directional motor control
• - Fault handling (sensor failure)
• - LCD/user interface integration