0cc273f83651aed9f502958bbcab99f45904dd7dLecture%204%20pdf.pdf

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1. ECE 270: Embedded Logic Design

2. Verilog

3. Verilog

4. Verilog: Module (Examples)

5. Verilog

6. Verilog:

7. Verilog: Module (Examples)

8. Verilog: Register

9. HDL Bits
•https://hdlbits.01xz.net/wiki/Step_one

10. Homework
•Using module for 2:1 mux (data flow level approach), design 8:1 mux via
module interconnections
•Design comparator for 2-bit inputs using data flow level approach.
•Using comparator for 1-bit inputs, design comparator for 2-bit inputs via
module interconnections