1 introduction to vlsi physical design

1. 1
Day 1
Introduction to VLSI Physical Design
Session Speaker
Ajaya Kumar.s

2. 2
©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
Session Objectives
„
To understand the Physical design flow
„
To understand the need for Physical design
„
To know about the tools used for physical design
„
To understand the concepts of CMOS process parameters
„
To know the issues of scaling and its effects

3. 3
©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
Session Topics
• Technology Evolution
• Scaling Issues
• Design Principles
• Verification and Simulation
• Detailed Physical Design Flow
• Foundry Files, Parameters, Rules and Guidelines

4. 4
©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
Technology Evolution: Cost and Integration
Drivers
„
Moore’s Law is about cost
„
Increased integration, decreased
cost Æmore possibilities for
semiconductor-based products
„
Pentium 4 die shot:
2.2cm

5. 5
©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
Sense of Scale (Scaling)
„
What fits on a VLSI Chip today?
„
State of the art logic chip {
20mm on a side (400mm
2
)
{
0.13mm drawn gate length
{
0.5μm wire pitch
{
8-level metal
„
For comparison {
32b RISC processor „
8K l x 16Kl
{
SRAM „
about 32l x 32l per bit
„
8K x 16K is 128Kb, 16KB
{
DRAM „
8l x 16lper bit
„
8K x16K is 1Mb, 128KB
20mm
(40,000 wire pitches)
320,000 l
0.13mm (2 l)
32b RISC Processor64b FP Processor
0.5mm (8 l)

6. 6
©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
MOS Transistor Scaling (1974 to present)
S=0.7
[0.5x per 2 nodes]
(Typical
MPU/ASIC)
Poly
Pitc
h
(Typical
DRAM)
Met
al
Pitc
h
ƒ
Decreased transistor/feature sizes Î
ƒ
Increased variability ( t
ox
, BEOL, DFM, SEU, etc.)
ƒ
Short channel effect, leakage power

7. 7
©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
SEMATECH Prototype BEOL stack, 2000
Wire
Via
Global (up to 5)
Intermediate (up to 4)
Local (2)
Passivation
Dielectric
Etch Stop Layer
Dielectric Capping Layer
Copper Conductor
with
Barrier/Nucleation
Layer
Pre Metal Dielectric
Tungsten Contact Plug
ƒ
Reverse-scaledglobal interconnects Î
ƒ
Growing interconnect complexity
ƒ
Performance critical global interconnects

8. 8
©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
Intel 130nm BEOL Stack
Intel 6LM 130nm process with
vias shown (connecting layers)
Aspect ratio = thickn ess / minimum width

9. 9
©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
Interconnect Capacitance: Parallel Plate Model
SiO
2
Substrate
L
W
T
H
ILD
ILD = interleveldielectric
Bottom plate of
cap can be
another metal
layer
C
int
= e
ox
* (W*L / t
ox
)

10. 10
©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
Line Dimensions and Fringing Capacitance
w
S
ƒ
Capacitive coupling Î
ƒ
Crosstalk effect
ƒ
Signal integrity
Lateral cap

11. 11
©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
Interconnect Evolution and Modeling Needs
„
Before 1990, wires were thick and wide while devices were big and slow {
Large wiring capacitances and device resistances
{
Wiring resistance << device resistance
{
Model wires as capacitances only
„
In the 1990s, scaling (by scale factor S) led to smaller and faster devices
and smaller, more resistive wires {
Reverse scaling of properties of wires
{
RC models became necessary
„
In the 2000s, frequencies are high enough that inductance has become a
major component of total impedance

12. 12
©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
Evolving Interconnects Affect Timing „
Interconnect capacitance > gate input capacitance {
Better prediction
„
Interconnect resistance no longer ignorable {
Better modeling: distributed R(L)C network, AWE, etc.
{
Effective capacitance< total load capacitance
„
Interconnect delay > gate de lay for sub-micron technologies

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©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
Sub-Wavelength Optical Lithography

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©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
…Complexity of Photomasks
How many wafers, on average, are printed with a mask set?

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©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
Summary of Technology Scaling
„
Scaling of 0.7x every three (two?) years
{
.25u .18u .13u .10u .07u .05u
{
1997 1999 2002 2005 2008 2011
{
5LM 6LM 7LM 7LM 8LM 9LM
„
Interconnect delay dominates system performance
{
consumes up to 70% of clock cycle
„
Cross coupling capacitance is dominating
{
cross capacitance Æ100%, ground capacitance Æ0%
{
ground capacitance is 90% in .18u
{
huge signal integrity implications (e .g., guardbandsin static analysis
approaches)
„
Multiple clock cycles required to cross chip
{
whether 3 or 15 not as important as fact of “multiple”> 1

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©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
New Materials Implications
„
Lower dielectric permittivity {
reduces total capacitance
{
doesn’t change cross-coupled / grounded capacitance proportions
„
Copper metallization {
reduces RC delay
{
avoids electromigration (factor of 4-5 ?)
{
thinner deposition reduces cross cap
„
Multiple layers of routing {
enabled by planarization; 10% extra cost per layer
{
reverse-scaled top-level interconnects
{
relative routing pitch may increase
{
room for shielding

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©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
Technical Issues
„
Manufacturability (chip can't be built)
{
antenna rules
{
minimum area rules for stacked vias
{
CMP (chemical mechanical polishing) area fill rules
{
layout corrections for optical proxi mity effects in subwavelength
lithography; associated verification issues
„
Signal integrity (failure to meet timing targets)
{
crosstalk induced errors
{
timing dependence on crosstalk
{
IR drop on power supplies
„
Reliability (design failures in the field)
{
electromigration on power supplies
{
hot electron effects on devices
{
wire self heat effects on clocks and signals

18. Noise
„
Analog design concerns are due to physical noise sources {
because of discreteness of electronic charge and
stochastic nature of electronic transport processes
{
example: thermal noise, flicker noise, shot noise
„
Digital circuits due to large, abrupt voltage swings, create deterministic
noise which is several orders of magn itude higher than stochastic physical
noise {
still digital circuits are prevalent because they are
inherently immune to noise
„
Technology scaling and performance de mands make noisiness of digital
circuits a big problem

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©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
Silicon Complexity Challenges Silicon Complexity Challenges
„
Silicon Complexity = impact of pr ocess scaling, new materials, new
device/interconnect architectures
„
Non-ideal scaling (leakage, power ma nagement, circuit/device innovation,
current delivery)
„
Coupled high-frequency devices and inte rconnects (signal integrity analysis
and management)
„
Manufacturing variability (library charac terization, analog and digital circuit
performance, error-tolerant design, la yout reusability, st atic performance
verification methodology/tools)
„
Scaling of global interconnect performance (communication,
synchronization)
„
Decreased reliability (soft error uncert ainty, gate insulator tunneling and
breakdown, joule heating and electromigration)
„
Complexity of manufacturing handof f (reticle enhancement and mask
writing/inspection flow, manufacturing NRE cost)

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©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
In a PDA…
„
Reference Design
: personal digital assistant (PDA)
„
Composed of CPU, DSP, peripheral I/O, and memory

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©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
…Implemented With an SoC
0.18um / 400MHz / 470mW (typical)
CPU
I-cache
32KB
D-cache
32KB
I2C
FICP
USB
MMC
UART AC97
I2S
OST
GPIO
SSP
PWM RTC
DMA controller
LCD
Cnt.
MEM
Cnt.
PWRCPG
SDRAM
64MB
Flash
32MB
LCD
Peripheral Area
4 – 48MHz
Data Transfer
Area
100MHz
Processor Area
Max 400MHz
MM Application
MP3
JPEG
Simple Moving Picture
6.5MTrs.
Available Time
6-10Hr
Specification
USB
MMC
KEY
Sound

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©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
Design Principles (Traditional)
„
Partition the problem (hirarchical design) {
Different abstraction levels: R TL, gate-level, switch-level,
transistor-level
„
Orthogonizeconcerns {
Abstraction vs. implementation
{
Logic vs. timing
„
Constrain the design space to simplify the design process {
Balance between design complexity and performance
{
E.g., standard-cell methodology

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©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
„
Integrate the problem (design closure) {
Back-annotation, predictability
„
Balance design metrics {
Area/timing/power/signal integrity/reliability
„
Explore the design space {
Balance between design complexity and performance
{
Platform-based SoC design
Design Principles(State of the Art)

24. 24
©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
Design Methodologies (+ business models)
„
Full-Custom (high effort, leading- edge performance, high-volume)
„
Semi-Custom (strong infrastructu re, economical in lower volumes) {
ASIC (Application-Specific Integrated Circuit)
{
Standard Cell/Gate Array/Via Programmable/Structured ASIC
„
FPGA
„
Special {
Analog (custom layout, I/Os and sense amps)
{
Mixed-Signal / RF (unique to each process, no scaling)
„
System-on-Chip (ÆSystem-in-Package) {
Various components: IP blocks, ASIC, FPGA, memory, uP, RF, etc.
{
Define implementation platform, hardware-software co-design
{
Performance vs. complexity

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©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
Flow
Schematic
Entry
Cell
Characterization
Layout
Entry
Standard Cell Library
3-D RLC
Modeling Tool
Wire Model
Device model
Layout rules
r,s, m
Layers
Synthesis Library (Timing/Power/Area)
C-Model
Verilog
Behavioral
Model
Verilog
Structural
RTL
Structural
Model
Parasitic Extraction Library
Place & Route Library (Ports)
Floorplan
Global
Layout
Block Layout
Floorplan
P & R
Functional
DRC/ERC/LVS
Static/Dynamic Timing w/extract
Functional
Static Timing
Power/Area Scan/Testability
Synthesis P & R
Clock Routing/Analysis

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©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
Test Generation
Design Verification
Timing Verification
Simulation
Floorplanning
Logic Partitioning
Die Planning
Logic
Synthesis
Logic Design and
Simulation
Behavioral Level Design
Global Placement Detail Placement
Clock Tree Synthesis
and Routing
Global Routing Detail RoutingPower/Ground
Stripes, Rings Routing
Extraction and
Delay Calc. Timing
Verification
LVS
DRC
ERC
IO Pad Placement
Traditional Taxonomy
Front End
Back End

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©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
Generic Flow Steps
„
Library preparation {
Library data preparation
{
Design data preparation
„
Logic design {
Specification to RTL
{
RTL simulation
{
Hierarchical floorplanning
{
Synthesis
{
Formal verification
{
Gate level simulation
{
Static timing analysis
„
Physical design
•
Physical floorplanning
•
Place and route
•
RC extraction
•
Formal verification
•
Physical verification
•
Release to manufacturing
„
Design for test
„
Engineering change order

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©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
Library and Design Data
„
Models and technology data requ ired to execute the design flow
„
Power, timing: ALF, DCL, OLA, .lib, STAMP
„
Layout: LEF, DEF, GDSII
„
Delays and path timing, parasitics: SDF, GCF, SDC, DSPF, RSPF,
SPEF, SPICE
„
Layout rules: Dracula, Calibre “deck”

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©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
„
Scheduling
{
Assignment of each operation to a time slot corresponding to a clock
cycle or time interval
„
Resource allocation
{
Selection of the types of hardwa re components and the number for
each type to be included in the final implementation
„
Module binding
{
Assignment of operation to the allocated hardware components
„
Controller synthesis
{
Design of control style and clocking scheme
„
Compilation
{
of the input specification language to the internal representation
„
Parallelism extraction
{
usually via data flow analysis techniques
„
…
High-Level Synthesis (Behavior ÆRTL)

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©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
Architecture Level Floorplanning
„
Defines the basic chip layout architecture {
Define the standard cell rows and I/O placement locations
{
Place RAMs and other macros
{
Separate gate array, memory, analog, RF blocks
{
Define power distribution structur es such as rings and stripes
{
Allow space for clock, major buses, etc.
„
Rules of thumb for cell density are us ed to initially calculate design size

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©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
Logic Synthesis
„
Conversion of RTL to gate-level netlist {
Targeted to a foundry-specific library
{
Can be performed hierarchically (block by block)
„
Timing-driven {
Clock information
{
Primary input arrival times, pr imary output required times
{
Input driving cells, output loading
{
False paths, multi-cycle paths
„
Interconnect delay may be calculate d based on a “wireload model”which
uses fanout to estimate delay
„
Clock parameters (insertion delay, sk ew, jitter, etc.) are assumed to be
attainable later in place and route

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©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
Formal Verification
„
RTL description and gate level netlist are compared to verify functional
equivalence, thereby veri fying the synthesis results {
Formal methods
{
Graph isomorphism
{
Binary Decision Diagram (BDD)
„
Emerging technology that supplement s the more traditional gate-level
simulation approach
„
FV also performed after place-and-route (if gate netlist changes)

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©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
RTL Simulation
„
RTL code, written in Verilog, VHDL or a combination of both, is
simulated to verify functional correctness
„
Testbenches apply input stimulus to the design
„
Several methods are used to verify the outputs {
Self-checking testbenches automatic ally verify output correctness
and report mismatches
{
Results can be stored in a file and compared to previous results
{
Waveform displays can be used to interactively verify the outputs

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©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
Gate-Level Simulation
„
Covers both functionality and timing
„
Correctness is only as good as the test vectors used
„
Especially critical for non-synchronous de signs, verification of false path and
multi-cycle path constraints
„
Cell timing is included in the simula tion models and interconnect delay is
passed from the synthesis run
„
Worst case PVT conditions are used to an alyze for setup violations, and best
case PVT conditions are used to analyze for hold violations {
PVT = Process, Voltage, Temperature

35. 35
©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
Static Timing Analysis
„
Verifies that design operates at desired frequency {
Implicitly assumes correct timing constraints (!), e.g., boundary
conditions
„
Timing constraints are similar to those used by logic synthesis
„
Verifies setup and hold times at FF i nputs; can also check timing from and
to PI’s and PO’s; can also check poin t-to-point delay values (with blocking
of pins, etc.)
„
As with gate-level simulation, both best- and worst-case analysis is
performed
„
Typically performed on full-chip (not block) basis {
May require modified constraints for inter-block issues: multiple clock
domains, multi-cycle paths, etc.
„
For compatibility with timing-driven la yout flow, helps to have simple /
single set of constraints {
Other issues: incremental analysis, …

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©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
Block-Level Physical Floorplanning
„
Reconcile logical and physical hierarchies
„
Cells that are interconnected want to be close together {
Take advantage of RTL hierarchy
{
Generate a physical hierarchy
{
RTL hierarchy = best physical hierarchy
„
Often bundled within the same co ckpit as the place and route tool
„
Give placement some initial clues to reduce complexity

37. 37
©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
Place and Route
„
Automatically place the standard cells
„
Generate clock trees
„
Add any remaining power bus connections
„
Route clock lines
„
Route signal interconnects
„
Design rule checks on the routes and cell placements
„
Timing driven tools {
Require timing constraints and analysis algorithms similar to those used
during the static timing analysis step

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©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
RC(L) Extraction
„
Calculate resistance and capacitance (and inductance) of interconnects {
Based on placement of cells
{
Routing segments
„
Calculate capacitive (inductive) ef fects of adjacent segments {
Extract capacitance between metal segments
„
RC(L) data transferred back to {
Static timing analysis (back annotation)
{
Gate level simulation
{
Replaces wire load model used in synthesis
„
Drive delay calculation, signal integrity analysis (crosstalk, other noise), static
timing
„
Q: How do parasitics and noise affect performance?

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©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
Physical Verification
„
DRC – Design Rule Check {
Spacing, min dimension rules
„
LVS – Layout Versus Schematic {
Verifies that layout and netlist are equivalent at the transistor level
„
Electrical Rule Check {
Dangling nets, floating nodes
„
GDSII (Stream Format) {
Final merge of layout, routing and placement data for mask
production

40. 40
©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
Release to Manufacturing
„
Final edits to the layout are made
„
Metal fill and metal stress relief rules are checked
„
Manufacturing information such as scri be lanes, seal rings, maskshop data,
part numbers, logos and pin 1 identifi cation information for assembly are
also added
„
DRC and LVS are run to verify the correctness of the modified database
„
‘Tapeout’documentation is prepared pr ior to release of the GDSII to the
foundry
„
Pad location information is prepar ed, typically in a spreadsheet
„
Cadence’s Virtuoso is used for cust om-manual edits of the mask layers
„
Manufacturing steps {
generation of masks
{
silicon processing
{
wafer testing
{
assembly and packaging
{
manufacturing test

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©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
More Design Metrics and Techniques
„
Area {
Cell area
{
Wirelength
„
Timing {
Gate
{
Interconnect
„
Power {
Dynamic
{
Static
{
Leakage
„
Signal Integrity {
Crosstalk (capacitive, inductive)
{
Supply voltage drop (IR drop,
LdI/dt)
„
Reliability {
Variation (Vdd, thermal, process
variation (tox, BEOL))
{
Electromigration
{
Hot electron effect (SEU)
ƒ
Cost minimization
z
Synthesis (technology mapping)
z
Placement, routing
ƒ
Performance optimization
ƒ
Logic transformation, transistor sizing
ƒ
Buffering, re-routing
ƒ
Power minimization
z
Gating (sleep transistors), variant Vdd
z
Process optimization
z
Dual-Vth
ƒ
Signal Integrity
z
Sizing, net ordering, shielding
z
P/G design, placement, synthesis
ƒ
Reliability
z
Statistical design optimization
z
Design margin

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©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
Wireload Model
„
Helps delay estimation at synthesis stage {
Gate delay = f(input slew, load cap)
{
Wire cap = f’(fanout number)
„
Empirical {
Different for each technology, library, tool,
design, and design stage
{
Statistical (from library), custom (multiple
iterations), structural (look at adjacent
nets) …
„
Large deviation remains {
Routing obstacles (hard IP blocks, macros,
etc.)
{
Routing algorithms/implementations (timing
driven, net ordering, details)
-10
-5
0
5
10
15
0 5 10 15
Design
% Est Error
2 5 10 15
#Pins
Cap

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©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
Interconnect Statistics
ƒ
What are some implications?
Local Interconnect
Global Interconnect
S
Local
= S
Technology
S
Global
= S
Die

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©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
Constructive Interconnect Prediction
„
Statistical models have their limitations
„
Critical paths and the law of small numbers {
Statistics properties, e.g., average wirelength
{
Extreme statistics properties, e.g., critical path length
„
Implementation details {
Routing congestion, e.g., horizontal effect
{
Timing optimization, e.g., layer assignment
{
Via blockage, pin accessability, wrong way routing, etc.
„
Predict by construction ( physical synthesis) {
try a fast (global) router

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©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
Goal: Design Convergence
„
What must converge? {
logic, timing, power, SI, reliability in a physical embedding
{
support front-end signoff with a predictable back-end
„
Achieve Convergence through Predictability {
correct by construction (“assume, then enforce”) „
constraints and assumptions pass ed downstream; not much goes
upstream
„
ignores concerns via guardbanding
„
separates concerns as able (e.g., FE logic/timing vs. BE spatial
embedding)
{
construct by correction (“tight loops”) „
logic-layout unification; synthesis- analysis unification, concurrent
optimization
{
elimination of concerns „
reduced degrees of freedom, pre-emptive design techniques
„
e.g., power distribution, layer assignment / repeater rules

46. 46
©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
Floorplan / Placement
Routing
„
Prototype delivers accurate physical
data
„
Levels of accuracy {
Placement-acknowledgeable
synthesis (PKS)
{
Including global route
{
Post-detailed-route (In-Place
Optimization, i.e., IPO)
„
Hierarchical timing budgeting: {
Chip-level CTS, top-level route
and IPO, power analysis and grid
design
{
Block-level synthesis, placement,
IPO, routing
„
“Handoff with enough physical
information to ensure correct results”
RTL
Gates
Physical Prototype
Functionality known
Timing / routability known
“Physical Prototyping Philosophy”

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©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
Power IR Drop
Analysis
Hierarchical Clock
Tree Synthesis
Full Chip Power
Planning
Block-Level
Optimization
Timing
Closure
150ps
skew
120ps skew
50ps
skew
50ps
skew
100ps
skew
130ps
skew
Place
Detailed Trial Route
RC Extraction
Delay Calc / STA
IPO
Full Chip
Physical
Prototype
Partition
“Tape Out Every Day”
Pictures of the Pieces…

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©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
Session Summary
•Technology and interconnect evolutions are the major sets for the
physical design
• New materials with respect to scaling are the key issues for the
physical design
•ASIC design flow like front end and backend with necessary inputs
from the foundry are the constrai nts involved in the process
After completing this session, students will be able