11. Parity Generator_Checker.pptx

ppt on parity checker

1. Combinational Circuits (Parity Bit Generators and Checkers)

2. Outline Parity - Even Parity - Odd Parity Parity Bit Generator Parity Checker

3. Parity In digital systems, when binary data is transmitted and processed , data may be subjected to noise so that such noise can alter 0s (of data bits) to 1s and 1s to 0s. The parity generating technique is one of the most widely used error detection techniques for the data transmission. Hence, parity bit is added to the word containing data in order to make number of 1s either even or odd. The message containing the data bits along with parity bit is transmitted from transmitter node to receiver node. At the receiving end, the number of 1s in the message is counted and if it doesn’t match with the transmitted one, then it means there is an error in the data.

4. Example : Odd Parity Generator / Checker

5. Parity Generator / Checker A parity generator is a combinational logic circuit that generates the parity bit in the transmitter. On the other hand, a circuit that checks the parity in the receiver is called parity checker . These are used in digital systems to detect the single bit errors in the transmitted data word. Parity systems Odd parity Even parity

6. Design of 3-bit Even P arity G enerator Step 1: Number of Inputs/Outputs Let the three inputs A, B and C are applied to the circuit and output bit is the parity bit P. The total number of 1s must be even, to generate the even parity bit P. Step 2: Truth Table

7. K-map Simplification Step 3: Logic Minimization

8. Step 4: Logic implementation Design of 3-bit Even P arity G enerator

9. Parity Generator / Checker Four-bit even- and odd-parity generators

10. Five bit even-parity checker

11. Even Parity Checker If any error occurs, the received message consists of odd number of 1s. The output of the parity checker is denoted by PEC (parity error check). The truth table for the even parity checker in which PEC = 1 if the error occurs, and PEC = 0 if no error occurs (sum of incoming data bits plus parity bit). truth table

12. K-Map Simplification

13. Logic Implementation

14. 17 Parity-Error Detection System

15. Activity 1 When the set of input data to an even parity generator is 0111, the output will be 1 Unpredictable Depends on the previous input

16. Activity 2 A staircase light is controlled by two switches one at the top of the stairs and another at the bottom of stairs: Make a truth table for this system. Write the logic equation is SOP form. Realize the circuit using AND-OR gates. Realize the circuit using NAND gates only.

17. Activity 3 Which data and parity bit combination is correct for an ODD parity data transmission system? data = 1110 0000 parity = 1 data = 0100 1010 parity = 1 data = 0000 0000 parity = 0 data = 1111 1111 parity = 1

18. Thank You!!