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fpga

1. 2022 IEEE International Symposium on Circuits and Systems
May 28- June 1, 2022 Hybrid Conference
An FPGA-based HW/SW Co-Verification
Environment for Programmable Network
Devices
Industrial Research Chair (IRC) for High Speed and Programmable Packet Processing
Polytechnique, Montreal (Kaloom-Intel-NoviFlow)
Mengyue Su, Jean- Pierre David, Yvon Savaria, Bill Pontikakis, Thomas Luinaud

2. 2
Content
Introduction
General Architecture
Methodology
Software Simulation
Hardware Implementation
Results& Comparisons
Conclusions& Future work

3. 3
Introduction
Software-Defined Network
Difficultyon program debugging
Simulation Verification PASSES
Implementation on FPGA FAILS
Timing Requirements cannot be
validated
Software/Hardware co-verification
Hardware Testbench

4. 4
General Architecture
Software testbench generates test data
Simulator providesbehavior information
Test data transfers to FPGA
FPGA used for verification (timing
requirements)
Comparison module provides full-test results
Data extraction in real-time
Platform used : NetFPGA -SUME
Blocks reused from the NIC* reference project
*https://github.com/NetFPGA/NetFPGA-SUME-public/wiki/NetFPGA-SUME-Reference-NIC -Vivado-2020.1-and -Ubuntu-2020.4

5. 5
Methodology-Software Simulation
Open-source tools
CocoTB*: Coroutine based Cosimulation
TestBench
GHDL*: Simulator for the VHDL
language
Capture data to be sentto FPGA
Recover data from FPGA
Data treatment and result comparison
Communication module: UART
Python provides high-levelprogrammability
*https://docs.cocotb.org/en/stable/
**https://github.com/ghdl/ghdl

6. 6
Methodology–UART Communication
Command-Response method
Each actionof each block linked to one
command
Received data is stored in a file
Control the transfer time of inserted data to
theDUT

7. 7
Methodology-Hardware Implementation
FIFO-basedblocks: insertion and extraction (with or without trigger signal)
Soft-processor (Microblaze):Builds the bridge betweenHostand FPGA data
blocks
Data transform between 32 bits (word) type and streaming type
Special extraction block: Support of triggerinput as anassertion signal
Data transferred before and after the assertion is captured
Insertion block : Data source selection
Data inserted from Host
Transparent

8. 8
Additional Counter Block
FIFO based counter block
Save the time difference between two packet
Save and reset counter when a new packet
arrive
Estimate the debit
Around 4000 cycles between 2 packets
Each packet takes 2 cycles
18Mbps

9. 9
Result & Comparison
FPGA resources used for each block (FIFO Depth: 1024) (Post-Implementation):
<0.5% LUT & FF
<1% BRAM
Simulation support : Results in high observability of internal signals
Cycle-accurate resolution : 6.4ns on NetFPGA-SUME
Data transfer rate of 10Gbps : Only one Ethernet port used in our test case
Targeted data replay : With the support of Assertion signals
All added blocks are white box and thus transparent in the system
ProposedTool FlueNT10G[1] OP4T[2] Formullar[3] XGT4[4]
Simulation Support Yes No No No No
Throughput 1x10 Gbit/s 3x10 or 4x10 Gbit/s - 1x10 Gbit/s 1x10 Gbit/s
PacketGeneration Partial Trace Replay No Yes Yes
PacketReplay (Targeted) Data Insertion Yes No Yes Yes
Precision 6.4 ns 6.4 ns 4 ns 6.4 ns 6.4 ns

10. 10
Conclusion & Future work
The first FPGA-basedSoftware/Hardware co-verification toolfor
configurable network applications
Cycle-accurate verification
•6.4ns for 156.25MHz frequency on NetFPGA-SUME
Lowresourceusage
•For 1024 deepFIFO, < 0.5% LUT & FF, < 1% BRAM
Future work
Integration with another FPGA platform
Addition of UserInterface (UI)

11. 11
Reference
[1]OELDEMANN,Andreas,WILD,Thomas,etHERKERSDORF,Andreas.FlueNT10G:AprogrammableFPGA-based
networktesterformulti-10-gigabitethernet.In:201828thInternationalConferenceonFieldProgrammableLogic
andApplications(FPL).IEEE,2018. p.178-1787.
[2]HAWARI,MohammedetCLAUSEN,Thomas.OP4T:BringingAdvancedNetworkPacketTimestampingintothe
Field.In:2021InternationalConferenceonInformationNetworking(ICOIN).IEEE,2021. p.137-142.
[3]PARK,Taejune,SHIN,Seungwon,SHIN,Insik,etal.Formullar:AnFPGA-basednetworktestingtoolforflexibleand
precisemeasurementofultra-lowlatencynetworkingsystems.ComputerNetworks,2021, vol.185,p.107689.
[4]JURACY,LeonardoR.,LAZZAROTTO,FelipeB.,PIGATTO,Daniel,etal.XGT4:anindustrialgrade,opensourcetester
formulti-gigabitnetworks.In:201724thIEEEInternationalConferenceonElectronics,CircuitsandSystems(ICECS).
IEEE,2017. p.252-255.