16148_flip-flopaaaaaaaaaaaaaaaaa1[1].ppt

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1. Flip Flops

2. Introduction
A sequential circuit consists of a feedback path, and employs some
memory elements.
2
Combinational
logic
Memory
elements
Combinational
outputs
Memory outputs
External inputs
Sequential circuit = Combinational logic + Memory Elements

3. Introduction
There are two types of sequential circuits:
synchronous: outputs change only at specific time
asynchronous: outputs change at any time
Bistable logic devices: latches and flip-flops.
A latch/flip-flop may have more than one input but it has only 2
outputs
One is normal output (Q) and the other is complemented output.
When the normal output is high (1), the state is called the SET
state
When the complemented output is high (1), the state is called the
RESET state
3

4. Synchronous sequential circuit:
is a system whose behaviour can be
defined from the knowledge of its
signals at discrete instants of time.
Asynchronous
sequential circuit:
Depends upon the
input signals at any
instant of time and
the order in which the
inputs change

5. Memory Elements
Memory element: a device which can remember value
indefinitely, or change value on command from its inputs.
Characteristic table:
5
Command
(at time t)
Q(t)Q(t+1)
Set X 1
Reset X 0
0 0Memorise /
No Change 1 1
command
Memory
element stored value
Q
Q(t): current state
Q(t+1) or Q
+
: next state

6. Memory Elements
Memory element with clock. Flip-flops are memory elements that
change state on clock signals.
Clock is usually a square wave.
6
command
Memory
element
stored value
Q
clock
Positive edges Negative edges
Positive pulses

7. Memory Elements
Two types of triggering/activation:
pulse-triggered
edge-triggered
Pulse-triggered
latches
ON = 1, OFF = 0
Edge-triggered
flip-flops
positive edge-triggered (ON = from 0 to 1; OFF = other time)
negative edge-triggered (ON = from 1 to 0; OFF = other time)
7
Positive edges Negative edges
Positive pulses

8. S-R Latch
Complementary outputs: Q and Q'.
When Q is HIGH, the latch is in SET state.
When Q is LOW, the latch is in RESET state.
For active-HIGH input S-R latch (also known as NOR gate latch),
R=HIGH (and S=LOW)  RESET state
S=HIGH (and R=LOW)  SET state
both inputs LOW  no change
both inputs HIGH  Q and Q' both LOW (invalid)!
8
R
S
Q
Q'

9. S-R Latch
Characteristics table for active-high input S-R latch:
9
SRQ Q'
00NCNC
No change. Latch
remained in present state.
101 0 Latch SET.
010 1 Latch RESET.
110 0 Invalid condition.
S
R
Q
Q'

10. S-R Latch
Active-HIGH input S-R latch
S-R Latch 10
R
S
Q
Q'
SR QQ'
10 10 initial
00 10(afer S=1, R=0)
01 01
00 01(after S=0, R=1)
11 00 invalid!
0
1
1
0
0
0
1
0
1
0
0
1
0
0
0
1
1
1
0
0

11. Edge-Triggered Flip-flops
Flip-flops: synchronous bistable devices
Output changes state at a specified point on a triggering input
called the clock.
Change state either at the positive edge (rising edge) or at the
negative edge (falling edge) of the clock signal.
Edge-Triggered Flip-flops 11
Positive edges Negative edges
Clock signal

12. Edge-Triggered Flip-flops
S-R, D and J-K edge-triggered flip-flops. Note the “>” symbol at the
clock input.
CS1104-11 Edge-Triggered Flip-flops 12
S
C
R
Q
Q'
S
C
R
Q
Q'
D
C
Q
Q'
D
C
Q
Q'
J
C
K
Q
Q'
J
C
K
Q
Q'
Positive edge-triggered flip-flops
Negative edge-triggered flip-flops

13. S-R Flip-flop
S-R flip-flop: on the triggering edge of the clock pulse,
S=HIGH (and R=LOW)  SET state
R=HIGH (and S=LOW)  RESET state
both inputs LOW  no change
both inputs HIGH  invalid
Characteristic table of positive edge-triggered S-R flip-flop:
CS1104-11 SR Flip-flop 13
X = irrelevant (“don’t care”)
 = clock transition LOW to HIGH
SRCLK Q(t+1)Comments
00 X Q(t)No change
01  0 Reset
10  1 Set
11  ? Invalid

14. S-R Flip-flop
It comprises 3 parts:
a basic NAND latch
a pulse-steering circuit
a pulse transition detector (or edge detector) circuit
The pulse transition detector detects a rising (or falling) edge and
produces a very short-duration spike.
CS1104-11 SR Flip-flop 14

15. S-R Flip-flop
The pulse transition detector.
CS1104-11 SR Flip-flop 15
S
Q
Q'
CLK
Pulse
transition
detector
R
Positive-going transition
(rising edge)
CLK
CLK'
CLK*
CLK'
CLK
CLK*
Negative-going transition
(falling edge)
CLK'
CLK
CLK*
CLK
CLK'
CLK*

16. D Flip-flop
D flip-flop: single input D (data)
D=HIGH  SET state
D=LOW  RESET state
Q follows D at the clock edge.
Convert S-R flip-flop into a D flip-flop: add an inverter.
CS1104-11 D Flip-flop 16
A positive edge-triggered D flip-
flop formed with an S-R flip-flop.
S
C
R
Q
Q'
CLK
D
DCLK Q(t+1)Comments
1  1 Set
0  0 Reset
 = clock transition LOW to HIGH

17. J-K Flip-flop
J-K flip-flop: Q and Q' are fed back to the pulse-steering NAND gates.
No invalid state.
Include a toggle state.
J=HIGH (and K=LOW)  SET state
K=HIGH (and J=LOW)  RESET state
both inputs LOW  no change
both inputs HIGH  toggle
CS1104-11 J-K Flip-Ffop 17

18. J-K Flip-flop
J-K flip-flop.
Characteristic table.
CS1104-11 J-K Flip-flop 18
J
Q
Q'
CLK
Pulse
transition
detector
K
JKCLK Q(t+1)Comments
00  Q(t)No change
01  0 Reset
10  1 Set
11  Q(t)'Toggle
QJK Q(t+1)
000 0
001 0
010 1
011 1
100 1
101 0
110 1
111 0
Q(t+1) = J.Q' + K'.Q

19. T Flip-flop
T flip-flop: single-input version of the J-K flip flop, formed by tying
both inputs together.
Characteristic table.
CS1104-11 T Flip-flop 19
TCLK Q(t+1)Comments
0  Q(t)No change
1  Q(t)'Toggle
QT Q(t+1)
00 0
01 1
10 1
11 0
Q(t+1) = T.Q' + T'.Q
T
Q
Q'
CLK
Pulse
transition
detector
J
C
K
Q
Q'
CLK
T

20. End of segment