730003648-Baseband-G3-1-HW-Presentation-CBC-Copy(2).pptx

Baseband-G3-1-HW-Presentation-CBC-Copy

1. Baseband G3.1 presentation Product intro

2. Digital Unit/Baseband DUL 20 DUG 20 DUW 30 DUS 41 LTE GSM WCDMA DUW 41 Baseband 5212/16 (GSM/WCDMA/LTE/NR) … Outdoor Baseband 6303/6502/ 6318 Micro B aseband 6502 19” Baseband 6620/30 2010 2015 2020 Baseband 6641/48 Radio Processor 6337/6347 Baseband 6621/31 Streetmacro 6701 ”G3” ”G2” ”G3.1” RAN Processor 6647/51 Radio Processor 6339/6353 2021

3. RA Baseband Backlog – October 2019 Baseband 6621/6631 Baseband 6641 4G/5G optimized 2/3/4/5G optimized Mixed GNSS Sync Radio P. 6337 Radio P. 6347 Streetmacro 6701 28GHz + 802.1x Sup. 802.1x Auth. Baseband 6648 RAN Processor 6647 RAN Processor 6651 Radio Processor 6353 Radio Processor 6339 Streetmacro 6701 39GHz Streetmacro 6705 28GHz Next Gen Streetmacro 2019 2020 2021 19.Q1 19.Q2 19.Q4 19.Q3 20.Q1 20.Q2 20.Q4 20.Q3 21.Q1 21.Q2 21.Q4 21.Q3 2022 22.Q1 22.Q2 22.Q4 22.Q3 Baseband R638/R608 BPU 25-50 “G4” KI K I CBC CBC CBC G3.1

4. RAN Compute portfolio Baseband 5212 / 5216 Baseband 6620 / 6630 Baseband 6303 Baseband 6318 Baseband 6502 Radio Processor 6347 Baseband 6641 Baseband 6648 Radio Processor 6337 New New New New Integrated solutions 6502 Micro Micro 6502 Streetmacro 6701 Baseband 6631 Baseband 6621 Radio Processor 6353 RAN Processor 6647 RAN Processor 6651 New New New New New Radio Processor 6339 New New New

5. Baseband 6641 Max Throughput: 5-7Gbps DL /2Gbps UL Mid-band Radio support: 3 sectors 100MHz, 16/8 layers High band support: 3 sectors, 400MHz, 2 layers Baseband 6648 Max Throughput: 10-15Gbps/3Gbps Mid-band Radio support: 3 sectors 200MHz, 16/8 layers High band support: 3 sectors, 800MHz, 2 layers Radio Processor 6337 Max Throughput: 5-7Gbps/2Gbps Mid-band Radio support: 3 sectors 100MHz, 16/8 layers High band support: 3 sectors, 400MHz, 2 layers Radio Processor 6347 Max Throughput: 10-15Gbps/3Gbps Mid-band Radio support: 3 sectors 200MHz, 16/8 layers High band support: 2-3 sectors, 800MHz, 2 layers Baseband G3(TTM) Indoor Outdoor

6. Gen 3.1 RAN Compute HWP requirements, (SW support for this will not be required in G3.1): Support for 256-bit ciphering och integrity protection. Throughput: 20Gbps on RAN Processor 6651 and Radio Processor 6353 10Gbps on RAN Processor 6647 and Radio Processor 6339. Outdoor Indoor RAN Processor 6651 ( MR 105 065-0937/05075) Radio Processor 6353 (MR 105 065-0937/05074) RAN Processor 6647 (MR 105 065-0937/05073) Radio Processor 6339 (MR 105 065-0937/05072) RAN Processor High Capacity RAN Processor Standard Capacity Radio Processor High Capacity Radio Processor Standard Capacity

7. HWP requirements, (SW support for this will not be required in G3.1): Support for 256-bit ciphering och integrity protection. Throughput: 20Gbps on RAN Processor 6651 and Radio Processor 6353 10Gbps on RAN Processor 6647 and Radio Processor 6339. General: All six G3.1 HW’s shall have SW support from the same SW release. HAL support between G3 and G3.1 is not needed. If G3.1 HW shall be Spareparts for G3 HW (in repairflow) will be decided later. G3.1 will however not support the same SW release. Requirements on G3.1

8. Baseband G3.1 products Baseband 6621 PRA Q2-21 19” indoor, 15 RI-ports, 1X Lynx 1.1 ASIC Baseband 6631 PRA Q2-21 19” indoor, 15 RI-ports, 2X Lynx 1.1 ASIC RAN Processor 6647 PRA Q3-21 19” indoor, 9 RI-ports, 2X Lynx 1.1 ASIC RAN Processor 6651 PRA Q3-21 19” indoor, 12 RI-ports, 4X Lynx 1.1 ASIC Radio Processor 6353 PRA Q3-21 Outdoor, rail mount, 9 RI-ports, 4X Lynx 1.1 ASIC Radio Processor 6339 PRA Q3-21 Outdoor micro BP, pole mount, 8 RI-ports, 2X Lynx 1.1 ASIC New product names Old: New: Baseband 6648 RAN Processor 6651 Baseband 6641 RAN Processor 6647 Radio Processor 6347 Radio Processor 6353 Radio Processor 6337 Radio Processor 6339 Kista CBC

9. LYNX brief LYNX is the next Generation Baseband ASIC Successor to the Trinity family The Lynx ASIC will be part of Multiple Baseband Module SAREK: 2 Lynx ASIC die 1 STRATIX 10 ND4 FPGA die 2 “E-tile” Transceiver die 22 25G Ethernet links 70x55 mm multi-chip package 165 W power dissipation 3 DDR4 IF on each LYNX FIVR voltage regulator on LYNX

10. What is lynx 1.1 The purpose of the Lynx 1.1 study is to propose ways of hardening logic originally proposed to reside in the FPGA part of the Lynx module To mitigate design risk and effort Reuse as much as possible from Lynx1.0 and Eagle Owl ASIC implementation. Reuse large portion of Lynx1.0 physical design.

11. What is lynx 1.1 LYNX with Integrated SerDes Interconnect (CPRI) Accelerators DLA Polar Prepared with interface towards a FPGA (2x25G) Possible to use in all products (BB6621/31/41/48 and RP6341/47) Monolithic implementation TUA integrated inside Lynx1,1 Arm core inside Lynx1.1 Lynx1.1 could replace SAREK modules BB6641/48 and RP 6341/47 will use SAREK in first release (TTM release). Lynx ICM BB Lynx ICM BB HBM HBM ND4 FPGA AIB E-Tile E-Tile AIB Lynx1.1 ICM BB D LA Polar TUA

12. Baseband 6648 and Radio Processor 6347 Baseline CPM3 ETH X CPU Radio Processor 6347 Lynx ICM BB Lynx ICM BB HBM HBM ND4 FPGA Lynx ICM BB Lynx ICM BB HBM HBM ND4 FPGA 6*25G 4x25G + 1x10G 2x25G ETH RI (CPRI/eCPRI) 3x25G 5x25G 4x25G + 1x10G CPM3 ETH X CPU Baseband 6648 Lynx ICM BB Lynx ICM BB HBM HBM ND4 FPGA Lynx ICM BB Lynx ICM BB HBM HBM ND4 FPGA 6*25G 4x25G + 1x10G 2x25G 6*25G 5x25G 4x25G + 1x10G AIB E-Tile E-Tile AIB AIB E-Tile E-Tile AIB AIB E-Tile E-Tile AIB AIB E-Tile E-Tile AIB BIM BIM 3x25G 4x25G 1x1G 3x25G 4x25G 1x1G

13. Lynx1.1 ICM BB Lynx1.1 ICM BB Lynx1.1 ICM BB Lynx1.1 ICM BB RAN Processor 6651 Radio Processor 6353 6x25G 6x25G 6x25G 3x25G CPM3 ETH X CPU CPM3 ETH X CPU Viggen Lynx1.1 ICM BB Lynx1.1 ICM BB Lynx1.1 ICM BB Lynx1.1 ICM BB Viggen 2x25G 1x10G 2x25G 1x10G 2x25G 1x10G 2x25G 1x10G 2x25G (4+1) x25G 2x25G (4+1) x25G 2x25G (4+1)x25G 2x25G (4+1) x25G 2x25G (4+1) x25G 2x25G (4+1)x25G 2x25G 1x10G 2x25G 1x10G 2x25G 1x10G 2x25G 1x10G 2x10G 2x10G 2x10G 2x10G 2x10G 2x10G 2x10G 2x10G ETH RI (CPRI/eCPRI) PCIe Gen3x4 PCIe Gen3x4 Lynx1.1 ICM BB D LA Polar TUA BIM PDCP PDCP PDCP 3x25G 4x25G 1x1G 3x25G 4x25G 1x1G RAN Processor 6651 and Radio Processor 6353 with Lynx 1.1

14. CPM3 ETH X CPU 1x1G (POE) 3x25G Radio Processor 6337 Lynx ICM BB Lynx ICM BB HBM HBM ND4 FPGA AIB 8*25G E-Tile ETH RI (CPRI/eCPRI) 2x25G + 1x10G CPM3 ETH X CPU 3x25G 4x25G Baseband 6641 Lynx ICM BB Lynx ICM BB HBM HBM xxxxxx FPGA 6*25G+3*25G 2x25G + 1x10G E-Tile AIB AIB E-Tile E-Tile AIB BIM BIM PCIe AVst PCIe AVst 1x1G Baseband 6641 and Radio Processor 6337 Baseline

15. Lynx1.1 ICM BB Lynx1.1 ICM BB CPM3 ETH X CPU RAN Processor 6647 Radio Processor 6339 3x25G 1x25G 1x10G 1x25G 1x10G 2x25G 6x25G 3x25G 4x25G 1x1G (POE) JAS PCIe Gen3x4 2x25G 4x25G Lynx1.1 ICM BB D LA Polar TUA ETH RI (CPRI/eCPRI) 1x10G 1x10G Lynx1.1 ICM BB Lynx1.1 ICM BB CPM3 ETH X CPU 1x25G 1x10G 1x25G 1x10G 3x25G 6x25G JAS PCIe Gen3x4 2x25G 4x25G 1x10G 1x10G PDCP PDCP BIM PDCP 1x1G RAN Processor 6647 and Radio Processor 6339 with Lynx 1.1

16. Lynx1.1 ICM BB Lynx1.1 ICM BB CPM3 ETH X CPU 3x10G 4x10G Lynx1.1 ICM BB CPM3 ETH X CPU Baseband 6631 and 6621 with Lynx 1.1 3x10G 4x10G 1x25G 1x10G 6x25G+ 9x10G 1x25G 1x10G 1x25G 1x10G 9x10G 6x25G 2x25G Baseband 6631 Baseband 6621 Flygande Tunnan JAS 1x1G 1x1G 4x25G PCIe Gen3x2 PCIe Gen3x4 ETH RI (CPRI/eCPRI) PDCP 1x10G 1x10G 1x10G PDCP Lynx1.1 ICM BB D LA Polar TUA BIM PDCP

17. Baseband 6621 block schematic

18. Baseband 6631 block schematic

19. RAN Processor 6647 block schematic

20. RAN Processor 6651/Radio Processor 6353 block schematic

21. Radio Processor 6339 block schematic

22. Use cases Arm inside

23. Interfaces

24. Front panel overview Baseband 6621 Baseband 6641/RAN Processor 6647 Baseband 6648/RAN Processor 6651 Baseband 6630/6620 (for reference ) Baseband 6631

25. CPM3 Short introduction in CPM3 as used in BB6648, BB6641, RP6347, RP6337 and many more… Fredrik Wildeqvist 2019-04-17

26. CPM3 vs. CPM2 Snow Ridge (x86 Atom cores) instead of AXM56xx (ARM) SMEM and CMEM merged. Two DDR4 interfaces (MEM0/1) LMT 100Mbps Ethernet PHY connected via PCIe instead of SGMII/RGMII FPGA Fast Passive Parallel (x8) configuration via GPIOs. CvP is still used via PCIe. CPM2 used loading via a SPI interface (PS). New SerDes for Ethernet; 25G Eth for IDL, TN and internal. New debug interfaces. DCI via USB3 New SPI boot. More memory and higher frequency. Quad mode, 48MHz. Dual SPI boot Flash. For update of FW in field with backup boot. UART interface to DCDC controller (PM). SPI was used in CPM2. SVID interface to power controller MTC is implemented in SNR using GPIOs. LEDs are controlled via registers in the PM (DCDC). USB Type-C at front.

27. CPM3 block diagram

28. Snow Ridge SNR 8c/12c/16c North die South die Number of Cores North: CPU & NAC South: PCH (or CDF; CederFork)

29. RAN P6 6 5 1 Floorplan SNR DDR4 Lynx Lynx Lynx Lynx BIM RI ABC RI DEF RI GHJ RI KLM TN BCD TN A USB&LMT SYNC&TN E ALA1&ALA2

30. BIM The functions overview Fan tray support, External Alarms, Retimers /SFP+ control for RI ports, F-Sync parts from TUF TUA backup including SPI, TUF SPI et cetera I2C for configuration of Lynx, SWRI Generic I/O pins et cetera, SWRI PCIe, new design block HWP for 256-bit ciphering och integrity protection

31. USB3 We use three USB3 interfaces (USB2 included). eUSB3 Drive. NAND Flash storage. 8GB (same as previous products) One USB3/2 interface at PTC connector. USB Type-C connector at front.

32. LMT interface At front of DU. RS232 and 100Mbit Eth. (+FSync) Much like previous generation. New is the i210 LMT PHY for Ethernet. Attached to PCIe on SNR. Contains a internal NonVolatile Memory. More like a OTP (One Time Programmable) memory. I.e. we can only update it a limited number of times. E.g. giving a new MAC address. 25MHz XTAL

33. RP6 6 5 1 HW requirement Building practice Capacity

34. RP6 6 5 1 Exploded view Heat spreader - Cu

35. RP6 353 Exploded view

36. RP6 339 Exploded view