8 Bit ALU

1. 8 Bit ALU Presented By : Chirag Vaidya (16MECV27) Yash Nagaria (16MECV15) 10/21/2016 1 8 Bit ALU Guided By : Dr. N. P. Gajjar

2. Contents : ALU Introduction Block Diagram Flowchart Verilog Code Test bench Simulation Synthesis report Device Utilization Summary Final Report Power and Thermal analysis Future scope 10/21/2016 2 8 Bit ALU

3. ALU Introduction : An arithmetic logic unit is a digital circuit used to perform arithmetic and logic operations. The following operations can be performed in ALU : Addition Subtraction Bitwise AND Bitwise OR Bitwise NOT Bitwise XOR Shift Left, Shift Right Rotate Left with Carry, Rotate Right Carry Checking the status of these flags C, AC, Z, S, P 10/21/2016 3 8 Bit ALU

4. Block Diagram of ALU : A B Operation Selection CMP -- ++ RL RR SL SR AND OR NOT EX-OR Out C Z S AC Arithmetic and Logical operation register out 10/21/2016 4 8 Bit ALU

5. Flow chart : Start Enter Data A , B S!=0 to 10 Output Display (invalid sel ) Sel = 0 to 10 yes no 10/21/2016 5 8 Bit ALU

6. Verilog Code : module alu8_bit(out , sel , C , AC , PE , S , Z); //input [7:0] A,B; input [3:0] sel ; output reg [7:0] out ; output reg C,AC,S,Z; output PE; reg [7:0] A = 8'b11000001; reg [7:0] B = 8'b00101001; always @( sel , A , B) begin case( sel ) 0: out = A & B; // BITWISE AND 1: out = A | B; // BITWISE OR 2: out = ~A; // BITWISE NOT 3: out = A^B; // EX-OR 4: out = A>>1; // SHIFT RIGHT 5: out = A<<1; // SHIFT LEFT 10/21/2016 6 8 Bit ALU

7. 6: begin C = A[0]; out = {C,A[7:1]}; // ROTATE RIGHT end 7: begin C = A[7]; out = {A[6:0],C}; // ROTATE LEFT end 8: begin { AC,out [3:0]} = A[3:0] + B[3:0] ; // Lower nibble addition with Auxillary Carry { C,out [7:4]} = A[7:4] + B[7:4] + AC; // Upper nibble addition with Carry S = out[7]; // Sign flag end 9: begin { AC,out [3:0]} = A[3:0] - B[3:0] ; // Lower nibble Subtraction with Auxillary Carry { C,out [7:4]} = A[7:4] - B[7:4] ; // Upper nibble Subtraction with Carry S = out[7]; // Sign flag end 10/21/2016 7 8 Bit ALU

8. // For CMP instructuion 10: begin { C,out [7:0]} = A[7:0] - B[7:0] ; // Upper nibble Subtraction with Carry { AC,out [3:0]} = A[3:0] - B[3:0] ; S = out[7]; // Sign flag if(out== 8'b0000_0000) begin Z <=1'b1; $display("A is equal to B"); end else if (C==0) begin $display("A is greater than B"); end else if (C==1) begin $display("A is less than B"); end end default : $display(" PLease enter valid selection"); endcase 10/21/2016 8 8 Bit ALU

9. if (out == 8'b0000_0000) begin Z <= 1'b1; end else begin Z <= 1'b0; end end even_parity m0(PE,A); endmodule module even_parity (out , in); input [7:0]in; output out; assign out=(in[0]^in[1]^in[2]^in[3]^in[4]^in[5]^in[6]^in[7]); endmodule 10/21/2016 9 8 Bit ALU

10. Test bench : module alu ; // Inputs reg [3:0] sel ; reg [7:0] A; reg [7:0] B; // Outputs wire [7:0] out; wire C; wire AC; wire PE; wire S; wire Z; // Instantiate the Unit Under Test (UUT) alu8_bit uut ( .out(out), . sel ( sel ), .C(C), .AC(AC), .PE(PE), .S(S), .Z(Z), .A(A), .B(B) ); 10/21/2016 10 8 Bit ALU

11. initial begin // Initialize Inputs sel = 0000; A = 8'b11001001; B = 8'b10001001; #1000 sel = 0; #1000 sel = 1; #1000 sel = 2; #1000 sel = 3; #1000 sel = 4; #1000 sel = 5; #1000 sel = 6; #1000 sel = 7; #1000 sel = 8; #1000 sel = 9; #1000 sel = 10; #1000; // Add stimulus here end endmodule 10/21/2016 11 8 Bit ALU

12. Simulation : 10/21/2016 12 8 Bit ALU

13. Synthesis report : HDL Synthesis Report Macro Statistics # Adders/ Subtractors : 5 4-bit adder carry in/out : 1 4-bit adder carry out : 1 5-bit subtractor : 2 9-bit subtractor : 1 # Latches : 11 1-bit latch : 11 # Multiplexers : 8 1-bit 11-to-1 multiplexer : 8 # Xors : 9 1-bit xor2 : 8 1-bit xor8 : 1 10/21/2016 13 8 Bit ALU

14. Device Utilization Summary : 10/21/2016 14 8 Bit ALU

15. Final report : Cell Usage : # GND : 1 # LUT2 : 15 # LUT3 : 21 # LUT4 : 63 # VCC : 1 # XORCY : 9 # Flip-flops/Latches : 19 # IO Buffers : 33 # IBUF : 20 # OBUF : 13 RTL Top Level Output File Name : alu8_bit.ngr Top Level Output File Name : alu8_bit Output Format : NGC Optimization Goal : Speed Keep Hierarchy : No Design Statistics IOs : 33 10/21/2016 15 8 Bit ALU

16. Power and Thermal Analysis : 10/21/2016 8 Bit ALU 16

17. Future Scope : We have designed 8 bit ALU , which can be used in many 8 bit µprocessor or µcontroller , also in SoC . We can do parallel processing operations using pipelining concept . 10/21/2016 17 8 Bit ALU

18. References : https://en.wikipedia.org/wiki/Arithmetic_logic_unit#Status https://community.arm.com/groups/processors/blog/2012/09/24/8-bit-versus-32-bit-mcus--the-impassioned-debate-goes-on https://en.wikipedia.org/wiki/ARM_architecture http://www.arm.com/products/processors/instruction-set-architectures/index.php 10/21/2016 18 8 Bit ALU

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