8085 instruction set.pptx hello world baby

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1. Microprocessor First Generation Between 1971 – 1973 PMOS technology, non compatible with TTL 4 bit processors  16 pins 8 and 16 bit processors  40 pins Due to limitations of pins, signals are multiplexed Second Generation During 1973 NMOS technology  Faster speed, Higher density, Compatible with TTL 4 / 8/ 16 bit processors  40 pins Ability to address large memory spaces and I/O ports Greater number of levels of subroutine nesting Better interrupt handling capabilities Intel 8085 (8 bit processor) Third Generation During 1978 HMOS technology  Faster speed, Higher packing density 16 bit processors  40/ 48/ 64 pins Easier to program Dynamically relatable programs Processor has multiply/ divide arithmetic hardware More powerful interrupt handling capabilities Flexible I/O port addressing Intel 8086 (16 bit processor) Fourth Generation During 1980s Low power version of HMOS technology (HCMOS) 32 bit processors Physical memory space 2 24 bytes = 16 Mb Virtual memory space 2 40 bytes = 1 Tb Floating point hardware Supports increased number of addressing modes Intel 80386 Fifth Generation Pentium 5

2. If you have a memory chip of size 256 kilobytes (256 x 1024 x 8 bits ), how many wires does the address bus need, in order to be able to specify an address in this memory? Note: the memory is organized in groups of 8 bits per location, therefore, how many locations must you be able to specify?

3. 256 KB = 2^18 bytes. A computer is generally made in byte-addressable format, ie , one bit in a logical address can be used to denote 1 Byte of physical memory address. Thus, if we go by byte addressable format, we get: log (base 2) 2^18 = 18. Thus, 18 bits are needed for the logical address to be specified. If you have a memory chip of size 256 kilobytes (256 x 1024 x 8 bits ), how many wires does the address bus need, in order to be able to specify an address in this memory? Note: the memory is organized in groups of 8 bits per location, therefore, how many locations must you be able to specify?

4. What is the memory organization of a computer with four 128*8 RAM chips and one 512*8 ROM chips? How many address lines are required to access the memory?

5. If a  memory size  is given as   m*n , m = number of words n = number of bits in a word (i.e. word length) Memory is usually designed to store or retrieve data in word-length quantities. Thus, one RAM chip of 128∗ 8  size has 128 words and 8 bits of each word. 128=2^7 Thus, 7 address bits are required for  1 RAM chip . We are given 4 RAM chips. Thus, to select each word separately 2^2=4 i.e. 2 more address bits are required. In total, 7+2=9  address bits  are needed for  4 RAM chips . Similarly, one ROM chip of 512∗8 size has 512 words and 8 bits of each word. 9 address bits  are required for  1 ROM chip . (Since, 2^9=512) Now to differentiate the addresses at ROM and RAM, we need another 1 address bit. In total, it works out to be 10 address bits and therefore,  10 address signals . What is the memory organization of a computer with four 128*8 RAM chips and one 512*8 ROM chips? How many address lines are required to access the memory?