8085 instructions and addressing modes

Detail Description of instrcutions and addressing modes of 8085

1. Addressing Modes
and Instruction Set of
8085
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2. Addressing Modes
•Addressingmodeisthemannerinwhichanoperand
isgiveninaninstruction.
•Operand:Thevalueonwhichprogrammerwantto
operate.
•Variousformatsforspecifyingoperandsarecalled
addressingmodes.
•Typesofaddressingmode:
▫ImmediateAddressing
▫RegisterAddressing
▫MemoryDirectAddressing
▫IndirectAddressing
▫ImplicitorImpliedAddressing
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3. Immediate Addressing
•Dataisgivenintheinstruction.
•Transferstheoperandgivenintheinstruction.
•Abyteorword–tothedestinationregisterormemory
location.
•Operandispartoftheinstruction.
•Operandisstoredintheregistermentionedinthe
instruction.
•Nomemoryreferencetofetchdata.
•Advantage:
▫Executesfaster
▫Simple
•Disadvantage:
▫Biginstruction(Size)
•Eg:ADI98H;MVIA25H.LXIH5000HEtc.
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4. Immediate Addressing
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Instruction
Opcode Operand
MVI A, 25
A
25H
25H

5. Register Addressing
•Thedataisgivenbyaregister.
•Transfersacopyofabyteorwordfromthesource
registertothedestinationregister.
•Operandisintheregisternamedintheinstruction.
•1byteinstruction.
•Theoperandiswithintheprocessor,sothe
executionisfaster.
•Advantage:
▫Faster
▫Smallsize
•Disavantage:
▫Verylimitedregisterspace.
▫Complex
•Eg:MOVA,B;ADDBetc,
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6. Register Direct Addressing
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Opcode Register Address
Registers, in CPU
Operand
Instruction
MOV A,B
B
A
65H
65H

7. Memory Direct Addressing
•Movesabyteorwordbetweenmemory
locationandregister.
•Thememoryaddressoftheoperandisgivenin
theinstruction.
•Doesnotsupportmemorytomemorytransfer.
•Advantage:
▫Simple
•Disadvantage:
▫Toolarge
▫Rigid
•Eg:STA9000H,LDA9500Hetc.
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8. Memory Direct Addressing
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Instruction
Opcode
Operand
Memory Address
Memory
STA 9000H
9000
A
45H
45H

9. Indirect Addressing
•Transfersabyteorwordbetweenaregisteranda
memorylocation.
•Addressofamemorylocationisstoredinaregister
whichisspecifiedintheinstruction.
•Theeffectiveaddressiscalculatedbytheprocessorusing
thecontentoftheregisterspecifiedintheinstruction.
•Usedtoaccessseriesoflocations.
•Advantage:
▫Flexible
▫Loops
•Disaadvantage:
▫Complex
•Eg:MOVA,M;LDAXRp;STAXRpetc.
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10. Indirect Addressing
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Opcode Register Address
Memory
Operand
Instruction
Memory address
to operand
Register

11. Implicit or Implied Addressing
•Wedon’tgivethedataoraddressintheinstruction.
•Instructionitselfspecifiesthedatatobeoperated
upon.
•Doesn’trequiredanyoperand.
•Usedonparticularoperand.
•Advantage:
▫Simple
▫Small
•Disadvantage:
▫Rigid
•Eg:CMA,XCHG,SPHL,XTHL etc.
CMA:
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A01HFFH

12. Quick Overview
•Immediate:
▫Data in the instruction.
▫MVI B, 40H B 40H
▫LXIB, 4000H BC 4000H
•Register:
▫Data is in the register.
▫MOV A,B [A] [B]
▫INR B [B] [B+1]
▫INX B [BC] [BC+1]
•Direct:
▫Address is in the instruction.
▫LDA 8000H [A] [8000]
▫STA 9000H [A] [9000]
•Indirect:
▫Address is in the register.
▫LDAX B [A] [BC]
▫STAX B [A] [BC]
•Implied:
▫Implied
▫STC CY 1
▫CMC CY CY
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13. Instruction Set
Aninstructionisabinarypatterndesignedinsideamicroprocessortoperform
aspecificfunction.
Theassemblylanguagemnemonicsarethecodesforthesebinarypatternsso
thattheusercaneasilyunderstandthefunctionperformedbythese
instructions.
Theentiregroupofinstructionsthatamicroprocessorsupportsiscalled
InstructionSet.
•BasedonthedesignoftheALUandthedecodingunit,themicroprocessor
manufacturersgenerallylistouttheinstructionsetfortheevery
microprocessormanufactured.
•Thepurposeofaninstructionsetistofacilitatethedevelopmentofefficient
programsbyusers.
•Theinstructionsetisbasedonthearchitectureoftheprocessor.
•Everyµphasitsowninstructionset.
•Instructionsetconsistofbothassemblylanguagemnemonicsand
correspondingmachinecode.
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14. Instruction Set of 8085
•Intel8085processorhasitsownsetofinstructionslisted
bothinmnemonicsandmachinecode,alsocalledas
objectcode.
•As8085isan8-bitprocessor.
•Themachinecodesfortheinstructionsarealso8-bits
wide.
•Ithas246instructions.
Eachinstructionisrepresentedbyan8-bitbinaryvalue.
These8-bitsofbinaryvalueiscalledOp-Codeor
InstructionByte
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15. Classification of Instruction Set
Instruction set
Based on functionality Based on length
DataTransferInstruction
ArithmeticInstructions
LogicalInstructions
BranchingInstructions
Stack/IOandMcControlInstructions
One –byte
instruction
Two-byte
instruction
Three-byte
instruction
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16. Classification of Instruction Set
•Basedonlength
▫One-ByteInstructions
▫Two-ByteInstructions
▫Three-ByteInstructions
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17. One-Byte Instructions
•Instructionsrequireonlyonebyteinmachine
language.
•Theseinstructionsjusthavethemachinecodeor
op-codetorepresenttheoperationtobe
performed.
•Eg:MOVA,B;ADDM;XRAAetc.
▫MOVA,B Opcode Onebyte
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18. Two-Byte Instructions
•Instructionsthatrequiretwobytesinmachine
code.
•The1
st
byte:Op-code,whichspecifiesthe
operationtobeperformed.
•The2
nd
byte:8-bitoperand,whichiseitheran
8-bitnumberoranaddress.
•Eg:MVIA,05H;ADI0FH;IN50Hetc.
▫ MVIA05H
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Opcode 8-bit Operand
Two Byte

19. Three-Byte Instructions
•Instructionrequirethreebytesinmachinecode.
•1
st
byte:Op-code,whichspecifiestheoperation
tobeperformed.
•2
nd
and3
rd
byte:16-bitoperand,whichiseither
an16-bitnumberoranaddress.
•Eg:LXIH8500H;JMP6900H,STA7900Hetc.
▫ STA79 00H
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Opcode Higher order
8-bit operand
Lower order
8-bit operand
Three Byte

20. Classification of Instruction Set
•BasedonFunctionality:
▫DataTransferInstruction
▫ArithmeticInstructions
▫LogicalInstructions
▫BranchingInstructions
▫Stack/IOandM/CControlInstructions
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21. Data Transfer Instructions
•These instructions move data between registers,
or between memory and registers.
•These instructions copy data from source to
destination.
•Sometime data stored directly in designated
location.
•While copying, the contents of source are not
modified.
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22. Data Transfer Instructions
•MOV B,C: Copy from source to destination.
•MVIC,05H: Load register C with the data 05H.
•LXI H,9000H: Load 9000H in HL register pair.
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SourceDestination 88H88H
[C] 05H05H
[B] [C]
[H] [L]
90 00H9000

23. Data Transfer Instructions
•MVI M,25H: Put the data in memory location.
•MOV M,C: Copy the value of C to memory
location.
•MOV C,M:
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[M]25H 25H
[M]
C80H
80H

24. Data Transfer Instructions
•LDA8800H:Loadthecontentofmemorylocation8800Hin
theAccumulator.
•STA2500H:Thecontentsofaccumulatorarecopiedintothe
memorylocationspecifiedbytheoperand.
•STAXB:Thecontentsofaccumulatorarecopiedintothe
memorylocationspecifiedbythecontentsoftheregisterpair.
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[8800]
AF[A]AF
[A][2500] 5858
[B] [C]
8589
[8589] [A]
6B6B

25. Data Transfer Instructions
Op-codeOperand Description
MOV Rd, Rs
M, Rs
Rd, M
Copy from source to destination.
MVI R,8 bit dataLoad register with 8bit data.
LDA 16-bit
address
Load the content of memory location in
the Accumulator.
STA 16 bit
address
The contents of accumulator are copied
into the memory location specified by
the operand.
STAX Rp The contents of accumulator are copied
into the memory location specified by
the contents of the register pair.
LXI Rp,16 bit
data
Load the register pair immediate.
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26. Arithmetic Instructions
•Oneofthedatausedinarithmeticoperationsis
storedinaccumulator.
•Resultisstoredinaccumulator.
•Arithmeticoperationscannotbeexecutedwithout
Acc.
•Theseinstructionsperformtheoperationslike:
▫Addition
▫Subtraction
▫Increment
▫Decrement
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27. Addition
•Any8-bitnumber,orthecontentsofregister,orthecontentsof
memorylocationcanbeaddedtothecontentsofaccumulator.
•Theresult(sum)isstoredintheaccumulator.
•Notwoother8-bitregisterscanbeaddeddirectly.
Op-code Operand Description
ADD R
M
Thecontentsofregisterormemoryareaddedto
thecontentsofaccumulator.
ADC R
M
Addwithcarry.Thecarrygeneratedfromthe
previousoperationisincorporatedinthis
addition.
ADI 05H The8-bitdataisaddedtothecontentsof
accumulator.
DAD B The16-bitcontentsoftheregisterpairareadded
tothecontentsofH-Lpair.Theresultisstoredin
H-Lpair.Iftheresultislargerthan16bits,then
CYisset.
DAA Decimaladjustafteraddition.Itonlyusedafter
addition.Thisinstructiondoesn'thaveany
operand.ItisonlyimpliedonAcc.
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28. Subtraction
•Any 8-bit number, or the contents of register, or the
contents of memory location can be subtracted from
the contents of accumulator.
•The result is stored in the accumulator.
•Subtraction is performed in 2’s complement form.
•If the result is negative, it is stored in 2’s
complement form.
•No two other 8-bit registers can be subtracted
directly.
•Example:SUB B, SUB M, SUI data
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29. Increment / Decrement
•The8-bitcontentsofaregisteroramemorylocationcan
beincrementedordecrementedby1.
•The16-bitcontentsofaregisterpaircanbeincremented
ordecrementedby1.
•Incrementordecrementcanbeperformedonany
registeroramemorylocation.
Op-codeOperand Description
INR R
M
Thecontentsofregisterormemory
locationareincrementedby1..The
resultisstoredinthesameplace.
INX R Thecontentsofregisterpairare
incrementedby1.Theresultis
storedinthesameplace.
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30. Logical Instructions
•Theseinstructionsperformlogicaloperationson
datastoredinregisters,memoryandstatusflags
withthecontentsofaccumulator.
•Theresultisstoredinaccumulator.
•Thelogicaloperationsare:
▫AND
▫OR
▫XOR
▫Rotate
▫Compare
▫Complement
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31. AND, OR, XOR
Op-codeOperand Description
ANA R
M
Thecontentsoftheaccumulatorarelogically
ANDedwiththecontentsofregisterormemory.
Theresultisplacedintheaccumulator.
ANI 8-bit dataThecontentsoftheaccumulatorarelogically
ANDedwiththe8-bitdata.Theresultisplaced
intheaccumulator.
ORA R
M
ThecontentsoftheaccumulatorarelogicallyOR
edwiththecontentsoftheregisterormemory.
Theresultisplacedintheaccumulator.
XRI 8-bit dataThecontentsoftheaccumulatorareXORed
withthe8-bitdata.Theresultisplacedinthe
accumulator.
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32. Rotate
•Each bit in the accumulator can be shifted either left or
right to the next position.
•RLC: Each binary bit of the accumulator is rotated left by
one position.
•RAL:Each binary bit of the accumulator is rotated left by
one position through the Carry flag.
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76543210
C
Accumulator
76543210
C
Accumulator

33. Rotate Cont..
▫RRC:Eachbinarybitoftheaccumulatorisrotated
rightbyoneposition.
•RAR:Eachbinarybitoftheaccumulatorisrotatedright
byonepositionthroughtheCarryflag.
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76543210
Accumulator
76543210
Accumulator
C
C

34. Rotate
Op-codeOperand Description
RLC None Eachbinarybitoftheaccumulatorisrotatedleft
byoneposition.BitD7isplacedinthepositionof
D0aswellasintheCarryflag.CYismodified
accordingtobitD7.
RAL None Eachbinarybitoftheaccumulatorisrotatedleft
byonepositionthroughtheCarryflag.BitD7is
placedintheCarryflag,andtheCarryflagis
placedintheleastsignificantpositionD0.CYis
modifiedaccordingtobitD7.
RRC None Eachbinarybitoftheaccumulatorisrotatedright
byoneposition.BitD0isplacedinthepositionof
D7aswellasintheCarryflag.CYismodified
accordingtobitD0.
RAR None Eachbinarybitoftheaccumulatorisrotatedright
byonepositionthroughtheCarryflag.BitD0is
placedintheCarryflag,andtheCarryflagis
placedinthemostsignificantpositionD7.CYis
modifiedaccordingtobitD0.
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35. Compare
•Any 8-bit data, or the contents of register, or
memory location can be compares for:
▫Equality
▫Greater Than
▫Less Than
with the contents of accumulator.
•The result is reflected in status flags.
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36. Compare
Op-codeOperand Description
CMP R
M
Thecontentsoftheoperand(registeror
memory)arecomparedwiththecontents
oftheaccumulator.Bothcontentsare
preserved.
Theresultofthecomparisonisshownbysettingtheflags
ofthePSWasfollows:
if(A)<(reg/mem):carryflagisset
if(A)=(reg/mem):zeroflagisset
if(A)>(reg/mem):carryandzeroflagsarereset.
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37. Compare
Op-codeOperand Description
CPI 8-bit dataThe8-bitdataiscomparedwiththecontents
ofaccumulator. Thevaluesbeing
comparedremainunchanged.
Theresultofthecomparisonisshownbysettingtheflags
ofthePSWasfollows:
if(A)<data:carryflagisset
if(A)=data:zeroflagisset
if(A)>data:carryandzeroflagsarereset
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38. Complement
•Thecontentsofaccumulatorcanbecomplemented.
•Each0isreplacedby1andeach1isreplacedby0.
Op-codeOperand Description
CMA None Thecontentsoftheaccumulatorare
complemented.Noflagsareaffected.
CMC None TheCarryflagiscomplemented.No
otherflagsareaffected.
STC None TheCarryflagissetto1.Nootherflags
areaffected.
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39. Stack/IO and M/C Control
•Stack:
▫PUSH
▫POP
•I/O:
▫IN
▫OUT
•M/C Control:
▫RIM
▫SIM
▫NOP
▫HLT
▫DI
▫EI
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40. I/O Operation
•DatawillonlyabletotransferviaAcc.
•Processordealswithonedeviceatatime.
•EachandeveryI/Odevicesaresignifiedby
address.
•TheI/Oaddressareknownasport.
•Itis8-bitaddress.
•Wecanattach2
8
ie.256deviceswitha
processor.
•IN40H:A[40H]
•OUT50HA[50H]
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41. Control Instructions
•The control instructions control the operation of
microprocessor.
OpcodeDescription Status Flags
NOP None Nooperationisperformed.The
instructionisfetchedanddecoded
butnooperationisexecuted.
HLT None TheCPUfinishesexecutingthecurrent
instructionandhaltsanyfurther
execution.Aninterruptorresetis
necessarytoexitfromthehaltstate.
DI None Disableinterrupt.Theinterruptenable
flip-flopisresetandalltheinterrupts
excepttheTRAParedisabled.
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42. Branching Instructions
•Thebranchinginstructionalterthenormalsequential
flow.Eg.JMP,CALL,RET,
•Theseinstructionsaltereitherunconditionallyor
conditionally.
Op-codeOperand Description
JMP 16-bit
address
Jump unconditionally.The program
sequenceistransferredtothememory
locationspecifiedbythe16-bitaddressgiven
intheoperand.
Jx 16-bit
address
Jumpconditionally.Theprogramsequence
istransferredtothememory location
specifiedbythe16-bitaddressgiveninthe
operandbasedonthespecifiedflagofthe
PSW.
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43. Jump Conditionally
Opcode Description Status Flags
JC Jump if Carry CY = 1
JNC Jump if No Carry CY = 0
JP Jump if Positive S = 0
JM Jump if Minus S = 1
JZ Jump if Zero Z = 1
JNZ Jump if No Zero Z = 0
JPE Jump if Parity
Even
P = 1
JPO Jump if Parity
Odd
P = 0
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