8086 modes

8086 modes

1. THE 8086 MICROPROCESSORS In
Minimum & Maximum mode

2. Pin layout of the 8086

Vss (GND)
AD14
AD13
AD12
AD11
AD10

ADS
AD8
AD7
AD6
ADS
AD4
AD3
AD2
AD1
ADO
NMI
INTR
CLK
Vss (GND)

Vee (+5V)
AD15

A16/S3
A17/S4
A18/85
A19/S6
BHE/S7
MN/MX MIN

RBRRGRBVSSRBR

&

MAX MODE

3. Minimum-Mode and Maximum-
Mode System

® The 8086 and 8088 microprocessors can be
configured to work in either of two modes:
+ The minimum mode — MN/MX = 1
+ The maximum mode - MN/MX = O
o The mode selection feature lets the 8088 or
8086 better meet the needs of a wide variety of
system requirement

o Minimum mode 8088/8086 systems are
typically smaller and contain a single processor.

o Depending on the mode of operation selected,
the assignment for a number of the pins on the

4. Minimum-Mode and Maximum-
Mode System (cont.)

Common signals ]

| Name Function Te |
AD7-ADO | Address/data bus Bidirectional,
3-state
A15-A8 | Address bus Quip, N-II
A19/S6- | Address/status Output, 0 0 Emo
A16/S3 3-state ° 0 Stack segment
MN/MX Minimum/maximum Input 1 9 Code orno segment
Mode control 1 1 Datasegment
RD Read control Output,
TEST Wait on test control
READY Wait state control
RESET System reset
NMI _Nonmaskable
Interrupt request
INTR Interrupt request Input
cLK System clock Input
Vec +5 V Input
GND Ground

Signals common to both minimum and maximum mode

5. Minimum-Mode and Maximum-
Mode System (cont.)

Minimum mode signals (MN/MX = Vo.)
Name Function Type
HOLD | Hold request Input
HLDA | Hold acknowledge | Output
WA Write contro! Output,
Istate
10/M 10/memory control | Output,
Istate
DT/R Data transmit/receive | Output,
Istate
DEN Data enable Output,
Istate
580 Status line Output,
state
ALE Address latch enable. | Output
INTA Interrupt acknowledge | Output

Unique minimum-mode signals

6. Minimum-Mode and Maximum-
| Mode System (cont.)

Maximum mode signals (MN/MX = GND)
Function

Request/grant bus Bidirectional
access control

Bus priority lock Output,
control 3-state

Bus cycle status Output,
state

Instruction queue Output
status

Unique maximum-mode signals

7. Minimum mode 8086 system

HH

mio
= omux.
wR

Ri

Fig 1.1. Minimum Mode 8086 System

8. Minimum mode 8086 system

® Ina minimum mode 8086 system, the microprocessor 8086 is operated in
minimum mode by strapping its MN/MX pin to logic 1.

® In this mode, all the control signals are given out by the microprocessor chip
itself. There is a single microprocessor in the minimum mode system.

® The remaining components in the system are latches, transceivers, clock
generator, memory and I/O devices.

æ The clock generator also synchronizes some external signal with the system
clock.

= It has 20 address lines and 16 data lines, the 8086 CPU requires three octal
address latches and two octal data buffers for the complete address and data
separation.

9. Minimum mode 8086 system continue...

® Latches : They are generally buffered output D-type flip-flops like 74LS373 or
8282. They are used for separating the valid address from the multiplexed
address/data signals and are controlled by the ALE signal generated by 8086.

® Trans-receivers are the bidirectional buffers and some times they are called as
data amplifiers. They are required to separate the valid data from the time
multiplexed address/data signals.

® They are controlled by two signals namely, DEN and DT/R.

——® The DEN signal indicates the availability of valid data over the address/data
lines. The DT/R signal indicates direction of data, i.e. from or to the processor.

® Usually, EPROM are used for monitor storage, while RAM for users program
storage. A system may contain //O devices.

10. Minimum Mode Pins

10Mor MIO _ | The IOM (8088) or the MIO (8086) pin selects memory or Y/O.

WR The wiite line is a strobe that indicates that the 8086/8088 is outputting data
to a memory or /O device.

INTA The interrupt acknowledge signal is a response to the INTR input pin.

ALE Address latch enable shows that the 8086/8088 address/data bus contains
address information.

DIR The data transmit/receive signal shows that the microprocessor data bus is

transmitting (DIR = 1) or receiving (DIR =0) data
DEN Data bus enable activates extemal data bus buffers.
HOLD The hold input requests a direct memory access (DMA).
HLDA
ss

Hold acknowledge indicates that the 8086/8088 has entered the hold state.

The SS0 status line is equivalent to the SO pin in maximum mode operation

of the microprocessor. This signal is combined with IM and DUR to
decode the function of the current bus cycle .

11. Status Pins

any) Sl so Function
0 0 0 Interrupt acknowledge
0 0 1 WOread
0 1 0 1/Owrite
0 1 1 Halt
1 0 0 Opcode fetch
1 0 1 Memory read
1 1 0 Memory write
1 1 1 Passive

12. Queue status

QS, | QS, Queue Status

00m) | 0 No Operation. During the last clock cycle, nothing was
taken from the queue.

0 1 | First Byte. The byte taken from the queue was the first
byte of the instruction.

1 (high) | 9 | Queue Empty. The queue has been reinitialized as a result
of the execution of a transfer instruction,

i i Subsequent Byte, The byte taken from the queue was a

| subsequent byte of the instruction,

13. Minimum Mode 8086 System (cont..)

fore
re PEN TE Lg ee | ARE a
AGE Pt
ADD /STATUS NE EP S28; x
ADD/DATA
RD
DEN

Read Cycle Timing Diagram for Minimum Mode

SEK Ka MOANLUSIVIR004

14. Minimum mode - READ

™ Hence the timing diagram can be categorized in two parts,
™ the timing diagram for read cycle

"the timing diagram for write cycle.

™ The read cycle begins in T1 with the assertion of address latch
enable (ALE) signal and also M / IO signal.

> During the negative going edge of this signal, the valid address
is latched on the local bus.

15. Minimum mode — READ continue...

= The BHE and AO signals address low, high or both bytes. From T1 to T4
, the M/IO signal indicates a memory or I/O operation.

m AtT2, the address is removed from the local bus and is sent to the

output. The bus is then tri-stated. The read (RD) control signal is also

activated in T2.

The read (RD) signal causes the address device to enable its data bus

drivers. After RD goes low, the valid data is available on the data bus.

æ The addressed device will drive the READY line high. When the
processor returns the read signal to high level, the addressed device will
again tri-state its bus drivers.

16. Minimum Mode 8086 System (cont..)
D LE, IT, ITy uy tr, |
Clk | 7 [7 7
AE ONE À
ADD / STATUS E. eo! S,-S, Je

ADD/DATA [A As À Valid data D,,— Dy

DT/R 1

Write Cycle Timing Diagram for Minimum Mode

AM Kein er NOMA LUSV12004 a

17. Minimum mode - Write

® A write cycle also begins with the assertion of ALE and the emission
of the address. The M/IO signal is again asserted to indicate a
memory or I/O operation. In T2, after sending the address in T1, the
processor sends the data to be written to the addressed location.

æ The data remains on the bus until middle of T4 state. The WR
becomes active at the beginning of T2 (unlike RD is somewhat
delayed in T2 to provide time for floating).

= The BHE and AO signals are used to select the proper byte or bytes
of memory or I/O word to be read or write.

æ The M/IO, RD and WR signals indicate the type of data transfer as
specified in table below.

18. Maximum mode 8086 system

Maximum Mode 5086 Een ( cont..)

Control bus

O

er Fr

‘Clk Reset 2

‘Genera CIk à

nerator E

y 3284 Ready |
5086

AD,-AD,,|

AA

DEN > I buffer

RD|| [cs WR

Peripherals

Maximum Mode 8086 System.

19. Maximum mode 8086 system continue...

® In the maximum mode, the 8086 is operated by
strapping the MN/MX pin to ground.

® In this mode, the processor derives the status signal S2,
S1, SO. Another chip called bus controller derives the
control signal using this status information .

® In the maximum mode, there may be more than one
microprocessor in the system configuration.

® The components in the system are same as in the
minimum mode system.

20. Maximum mode 8086 system continue...

® The basic function of the bus controller chip IC8288, is to
derive control signals like RD and WR ( for memory and
V/O devices), DEN, DT/R, ALE etc. using the information
by the processor on the status lines.

= The bus controller chip has input lines $2, $1, SO and
CLK. These inputs to 8288 are driven by CPU.

® It derives the outputs ALE, DEN, DT/R, MRDC, MWTC,
AMWC, IORC, IOWC and AIOWC. The AEN, IOB and
CEN pins are specially useful for multiprocessor systems.

21. Maximum mode continue...

æ AEN and IOB are generally grounded. CEN pin is usually tied to +5V. The
significance of the MCE/PDEN output depends upon the status of the IOB
pin.

® If IOB is grounded, it acts as master cascade enable to control cascade
8259A, else it acts as peripheral data enable used in the multiple bus
configurations.

= INTA pin used to issue two interrupt acknowledge pulses to the interrupt
controller or to an interrupting device. IORC, IOWC are I/O read command
and I/O write command signals respectively . These signals enable an IO
interface to read or write the data from or to the address port.

æ The MRDC, MWTC are memory read command and memory write
command signals respectively and may be used as memory read or write
signals.

® All these command signals instructs the memory to accept or send data from
or to the bus.

® For both of these write command signals, the advanced signals namely
AIOWC and AMWTC are available.

22. Maximum-Mode Interface (cont.)

= 8288 bus controller

82 si Function

0 0 0 Interrupt acknowledge
0 0 1 1/0 read

0 1 0 1/0 write

0 1 1 Halt

1 0 0 Opcode fetch

A 0 1 Memory read

1 1 0 Memory write

1 1 i Passive

Bus status code

23. Memory Control Signals

® Maximum-mode memory con
= MRDC - Memory Read Comm
= MWTC - Memory Write Comm

(cont.)

rol signals
and

and

. Status Inputs
CPU Cycle 8288 Command
515 | &
o o o Interrupt acknowledge INTA
o | o | 1 | Read 1/0 port TORC
o 1 o Write 1/0 port TOWC, ATOWC
o [1 | | Ha None
1 | 0 | 0 | instruction fetch MRDC
1 o 1 Read memory MRDC
ı |» | 0 | Write memory MWTC, ANWC
aE

Passive

|

24. Maximum Mode 8086 System ( cont..)

ae PS fes

Ai a

Clk

AL

E 2 e

5-5, Active XE > XX Active
Add/Status O O
Add/Data = --------- (Ash Dem

MRDC A TEE TEIL
DT/R Sri ORIEN se ct OU A

Memory Read Timing in Maximum Mode

25. Maximum Mode 8086 System ( cont..)

7, One bus yee ——,
Clk
ALE /
555 Active X.
ADD/STATUS __ X _XBHEI SH men
ADD/DATA AısAoX_ Data out Djs-D;
a a rear O a
AIOWC >
MWTC or IOWC De ih A Berna ee LOBE Keen,

DT/R high-
DEN N /

Memory Write Timing in Maximum mode.

26. Isolated Input/Output Interface

NO device
0

1/O device
1

1/0 interface
circuitry

Veo,

1/0 device
N

Minimum-mode 8086 system I/O interface

27. Isolated Input/Output Interface (cont.)

086

IH
i

Maximum-mode 8086 system I/O interface

28. Isolated Input/Output Interface (cont.)

Status inputs
CPU cycle 8288 command

interrupt acknowledge

Read 1/0 port
Write VO port
Halt

Instruction fetch

Read memory
Write memory

Passive

LO bus cycle status codes

29. Input/Output Bus Cycles (cont.)

ONE BUS CYCLE
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30. Input/Output Bus Cycles (cont.)

ONE BUS CYCLE:
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