8LowPowerVLSI THIRD MODULE 2019 SCHEME.pdf

Low power vlsi

1. EC464: LOW POWER VLSI
Module-3
Power Reduction Techniques–
SupplyvoltageScalingApproaches:MultiVDDandDynamic
VDD,leakagepowerreductionTechniques–Transistorstacking,
VTCMOS,MTCMOS, DTCMOS,Powergating,Clockgatingfor
Dynamicpowerdissipation,TransistorandGateSizingfor
DynamicandLeakagePowerReduction.

2. Circuit techniques for leakage power reduction
WiththecontinuousscalingofCMOSdevices,leakagecurrentisbecoming
amajorcontributiontototalpowerconsumption.
Incurrentdeepsub-micrometerdeviceswiththresholdvoltages,sub-
thresholdandgateleakagehavebecomedominantsourcesofleakage.
Oneofthemostchallengingaspectsoftoday’sCMOSVLSIcircuitsis
standbypowerdissipation.Featuresizereductionhasmadetheeffectsof
leakagecurrentsmorepronounced.
Thevariouscircuittechniquesforleakagepowerreductionare,
Standbyleakagecontrolusingtransistorstacks,
multipleVthtechniques,
dynamicVthtechniques,
supplyvoltagescalingtechniques,
minimizingshortchanneleffect

3. Standby leakage control using transistor stacks :
Stack Effect
SubthresholdcurrentdependsexponentiallyonVT,VDS,andVGS.Thereforeit
isafunctionoftheterminalvoltages,VD,VB,VS,andVG.
Thismeansthattoknowthesub-thresholdleakageofadevicethebiasing
conditionshouldbeknown.
Bycontrollingtheterminalvoltagesthesub-thresholdleakagecanbecontrolled.
Inputpatternofeachgateaffectsthesub-thresholdaswellasthegateleakage
current.Theleakageoftransistorsinastackisafunctionofno.oftransistors
andinputpattern.
Sourcebiasingisthegeneraltermforseveraltechniquesthatchangethevoltageatthe
sourceofatransistor.ThegoalistoreduceVGS,whichhastheeffectofexponentially
reducingthesub-thresholdcurrent.
AnotherresultofraisingthesourceisthatitalsoreducesVBS,resultinginaslightly
higherthresholdvoltageduetothebodyeffect.
Thesimplestexampleofsourcebiasingoccurswhen“off”transistorsarestackedin
series.

4. Conceptually,thesourcevoltageoftheuppertransistorwillbealittle
higherthanthesourcevoltageofthelowertransistorsinthestack.
HenceVGSofuppertransistorisnegative,VBSisnegativeresultingin
increaseinthresholdvoltageandVDSisalsolower.
Duetothis,theleakageofuppertransistorreduces.Thisreductionis
calledstackeffect.
Butthisreductioninleakagecomesatanincreaseindelayperformance.
Thereductioninleakageduetostackeffectcanleadtoincreaseindelay
Hencecanbeusedinsituationswherethisdelaycanbetoleratedorby
usinggateswithnaturalstack.
Fig.1showsfournMOSdevicesofa4-inputNANDgateinastack.

5. 0 V
0 V
0 V
0 V 14mV
34mV
89mV
2.3V Fig.1 (a) A 4-input NAND gate (b) Source voltages of the nMOS
transistors in the stack

6. Fig.2showsathreenMOSdevicesofa3-inputNANDgateinastack.
Table1showstheinputvectorsandcorrespondingleakagecurrentsforthe3-
inputNANDgate.
Itcanbefoundthattheleakagecurrentisminimumfortheinputvector“000”.
Theleakagecurrentincreasesprogressivelywithincreaseinnumberofone’s.
Theleakagecurrentismaximumwhenallthebitsare‘1’.i.e.,fortheinput
vector“111”.
Fig.2:AthreenMOSdevicesof
a3-inputNANDgateinastack.
State
(ABC)
Leakage Current
(nA)
Leaking
Transistors
000 0.095 Q1, Q2, Q3
001 0.195 Q1,Q2
010 0.195 Q1,Q3
011 1.874 Q1
100 0.184 Q2,Q3
101 1.220 Q2
110 1.140 Q3
111 9.410 Q4,Q5,Q6
Table : Input vectors and corresponding
leakage currents for the 3-input NAND gate

7. Multiple Vth techniques
In this approach, MOSFETs with two different threshold voltages are used in a single chip.
It uses two operational modes-activeand sleepfor efficient power management.
A 2-input NAND gate MTCMOS circuit is shown in Fig. 3. VDD
Low-Vt
Transistors
CV1
CV2
SL
SL
Q1
Q2
Q1Q2&- Sleep transistors.
VDDV
GNDV
GND
Fig. 3 MTCMOS basic structure.

8. TheCMOSlogicgateisrealizedwithtransistorsoflowthresholdvoltageofabout0.2-
0.3V.
Insteadofconnectingthepowerterminallinesofthegatedirectlytothepowersupply
linesV
ddandGND,heretheseareconnectedtothe‘virtual’powersupplylines(VDDV
andGNDV).
TherealandvirtualpowersupplylinesarelinkedbytheMOStransistorQ
1&Q
2.These
transistorshavehighthresholdvoltageintherange0.5-0.6Vandserveassleepcontrol
transistors.
Innormalmode,theNANDgateoperatesatahighspeedcorrespondingtothelow
thresholdvoltageof0.2V,whichisrelativelylowcomparedtothesupplyvoltageof
1.0V.
Insleepmode,SLissettoHIGHtoturnbothQ
1
andQ
2
OFF,therebyisolatingthereal
supplylinesfromVDDVandGNDV.
Asthesleeptransistorsarehavinghighthresholdvoltage(0.6V),theleakagecurrent
flowingthroughthesetwotransistorswillbesignificantlysmallerinthismode.
Asaconsequence,leakagepowerconsumptionduringthestand-byperiodcanbe
dramaticallyreducedbysleepcontrol.

9. Dynamic Vth techniques
Variable-threshold-voltage CMOS (VTCMOS) approach
Wehaveobservedthatlowsupplyvoltagealongwithlowthresholdvoltage
providesreducedoverallpowerdissipationwithoutdegradationin
performance.
However,useoflow-V
ttransistorsinevitablyleadtoincreasedsub-threshold
leakagecurrent,whichisofmajorconcernwhenthecircuitisinstandby
mode.
Inmanyrecentapplications,suchascellphone,PDAs,etc,majorpartofthe
circuitremainsinstandbymodemostofthetime.
Ifthestandbycurrentisnotlow,itwillleadtoshorterbatterylife.
VTCMOScircuitsmakeuseofthebodyeffecttoreducesubthresholdleakage
current,whenthecircuitisinnormalmode.
Weknowthatthethresholdvoltageisafunctionofthevoltagedifference
betweenthesourceandthesubstrate.
ThesubstrateterminalsofallthenMOStransistorsareconnectedtotheground
potentialandthesubstrateterminalsofallthepMOStransistorsareconnected
toV
dd,asshowninFig.4.

10. n+p+ n+ p+ p+n+
n-well
p substrate
n+p+ n+ p+ p+n+
n-well
p substrate
Bias
Bias Fig 4 (a) Physical structure of a CMOS inverter without body bias, (b) with body bias

11. Thisensuresthatthesourceanddraindiffusionregionsalwaysremainreversed
biasedwithrespecttothesubstrateandthethresholdvoltagesofthetransistorsare
notsignificantlyinfluencedbythebodyeffect.
Ontheotherhand,incaseofVTCMOScircuits,thesubstratebiasvoltagesof
nMOSandpMOStransistorsarecontrolledwiththehelpofasubstratebiascontrol
circuit,asshowninFig.5.V
out
substrate bias
control circuit
V
in
V
dd=1v
Fig 5 Substrate bias control circuit

12. Whenthecircuitisoperatingintheactivemode,thesubstratebiasvoltages
fornMOSandpMOStransistorsare??????
??????�=0??????and??????
??????�=??????
????????????.
Assumingthat??????
????????????=1V,thecorrespondingthresholdvoltagesforthenMOS
transistorsandpMOStransistorsare??????
??????�=0.2??????and??????
??????�=−0.2??????
respectively
Ontheotherhand,whenthecircuitisinstandbymode,thesubstratebias
controlcircuitgeneratesalowersubstratebiasvoltageof??????
??????�=−??????
??????forthe
nMOStransistorandahighersubstratebiasvoltage??????
??????�=??????
????????????+??????
??????forthe
pMOStransistors.
ThisleadstoincreaseinthresholdvoltagesfornMOSandpMOStransistors
to??????
??????�=0.5??????and??????
??????�=−0.5??????respectively
This,inturn,leadstosubstantialreductioninsubthresholdleakagecurrents
becauseoftheexponentialdependenceofsubthresholdleakagecurrenton
thethresholdvoltage.
Ithasbeenfoundthatforevery100mVincreaseinthresholdvoltage,the
subthresholdleakagecurrentreducesbyhalf.

13. AlthoughVTCMOStechniqueisaveryeffectivetechniqueforcontrolling
thresholdvoltageandreducingsubthresholdleakagecurrent,itrequires
twinwellortriple-wellCMOSfabricationtechnologysothatdifferent
substratebiasvoltagescanbeappliedtodifferentpartsofthechip.
Separatepowerpinsmaybealsorequiredifthesubstratebiasvoltage
levelsarenotgeneratedonchip.
Usually,theadditionalarearequiredforthesubstratebiascontrolcircuitry
isnegligiblecomparedtotheoverallchiparea.

14. Supplyvoltage scalingtechniques
Voltagescaling.Acommonandveryeffectivemethodofreducingthepower
dissipationofacircuitistoreduceitssupplyvoltage.
Thedynamicpowerdissipationcomponentisdirectlyproportionalto??????????????????
2
that
makesthistechniquesoeffective.
Thesupplyvoltagescalingalsohelpstoreducethestaticpower.
Thisisbecausethesubthresholdleakagepowerdecreasesduetothereduction
of
thedrain-inducedbarrierlowering(DIBL),
thegate-induceddrainleakage(GIDL),and
thegatetunnelingcurrentaswell.

15. TheswitchingpowerdissipationinCMOSdigitalintegratedcircuitsisa
strongfunctionofthepowersupplyvoltage.
Therefore,reductionofVDDemergesasaveryeffectivemeansoflimitingthe
powerconsumption.
PipeliningApproach
First,considerthesinglefunctionalblockshowninFig.whichimplementsa
logicfunctionF(INPUT)oftheinputvector,INPUT.
Boththeinputandtheoutputvectorsaresampledthroughregisterarrays,
drivenbyaclocksignalCLK.
Assumethatthecriticalpathinthislogicblock(atapowersupplyvoltageof
VDD)allowsamaximumsamplingfrequencyoffCLK;
inotherwords,themaximuminput-to-outputpropagationdelaytP,maxofthis
logicblockisequaltoorlessthanTCLK=1/fCLK.
Fig.alsoshowsthesimplifiedtimingdiagramofthecircuit.Anewinput
vectorislatchedintotheinputregisterarrayateachclockcycle,andthe
outputdatabecomesvalidwithalatencyofonecycle.

17. The dynamic power consumption of this structure can be found as
NowconsideranN-stagepipelinedstructureforimplementingthesame
logicfunction,asshowninFig..
ThelogicfunctionF(INPUT)hasbeenpartitionedintoNsuccessivestages,
andatotalof(N-1)registerarrayshavebeenintroduced,inadditiontothe
originalinputandoutputregisters,tocreatethepipeline.
Allregistersareclockedattheoriginalsamplerate,fCLK.
ThenthelogicblocksbetweentwosuccessiveregisterscanoperateN-times
slowerwhilemaintainingthesamefunctionalthroughputasbefore.
Thisimpliesthatthepowersupplyvoltagecanbereducedtoavalueof
VDD,new,toeffectivelyslowdownthecircuitbyafactorofN.
ThedynamicpowerconsumptionoftheN-stagepipelinedstructurewitha
lowersupplyvoltageandwiththesamefunctionalthroughputasthesingle-
stagestructurecanbeapproximatedby

19. Parallel processing

20. Deep submicron devices design issues
Scaling down feature size is an important issue for high-performance and
high-density circuits.
However, some second order effects become serious for short-channel
devices.
The reduction of short channel effect (SCE), has become a major challenge in
deep sub-micrometer devices and circuits.
The important SCE includes,
Threshold voltage roll-off and
Drain induced barrier lowering (DIBL),

21. Short-channel threshold voltage roll-off
•Fig.6 shows a schematic of a MOS transistor. Here L is the channel length and Xj
is the source and drain junction depth
Fig.6 A schematic of a MOS transistor.

22. •The surface potentials of short channel and long channel devices before strong
inversion are shown in fig.7. The drain, source and body voltages are all zero.
Fig.7 The surface potentials of short channel and long channel devices (Vd=0V)

23. For a long channel transistor, the barrier is constant.
As for a short channel device, the barrier is reduced along with the scaling
of the channel length.
Therefore, the smaller the channel length, the lower the threshold voltage.
The relationship between threshold voltage and transistor channel length is
shown in fig. 8
Fig.8Thresholdvoltageversuschannellength.Inordertomakethedeviceworkproperly,
dVth/dLcannotbetoolarge.Thiswilldeterminetheminimumchannellength(Lmin)

24. Drain-induced barrier lowering
•Fig.9showsthesurfacepotentialsoflong-channelandshort-channel
devicesatalargedrainvoltage(Vd).
•Foralong-channeldevice,thebarrierisnotsensitivetoVd.However,the
barrierofashort-channeldevicewillreducealongwiththeincreaseof
drainvoltage,whichwillcauseahighersubthresholdcurrentandlower
thresholdvoltage.
Fig. 9 The surface potentials of short channel and long channel devices (Vd> 0V)

25. Minimizing short channel effect
•In order to minimize a short-channel effect, a sufficient large aspect ratio (AR) of the
device is required. AR is defined as,
AR=DIMENSIONlateral/DIMENSIONvertical (1)
ForaMOSFET,ARcanbeexpressedas
Whereє
????????????andє
�??????arethesiliconandoxidepermittivities
•L, ??????
�??????, d, ??????
??????are channel length, gate oxide thickness, depletion depth and junction
depth respectively.
•From the above equation, we can see that reducing will reduce the SCE of a
MOSFET. In order to minimize SCE, a modified MOSFET structure can be used.
•Fig. 10 shows the low-impurity channel shallow-junction MOSFET

26. Fig.10 Low-impurity channel shallow-junction MOSFET
The small SCE of this transistor is because of the small depletion depth and
junction depth.
The AR of a single gate silicon-on-insulator (SOI) MOSFET is shown in
fig.11.

27. •Since d =??????
??????, the AR is given by
Fig.11 A single-gate SOI MOSFET

28. •Fig. 12 shows a double-gate silicon-on-insulator (DGSOI) MOSFET. The AR of
DGSOI MOSFET is
Fig.12 A DGSOI MOSFET
Itisclearthattheeffectivejunctiondepthandthedepletionwidtharereducedtohalfofthat
ofabulkMOSFET.
Therefore,theSCEofaDGSOIMOSFETismuchsmallerthanabilksiliconMOSFET,
whichmakesitagoodcandidatefordeepsubmicrometerapplications.
Short channel threshold voltage roll-off and DIBL are two short-channel effects, which will
complicate the transistor operation

29. Power vs Clock Gating
Clockgatingfocusesonthedynamicpowerofthecircuitby
reducingtheswitchingfrequency
Powergatingfocusesonthestatic/leakagepowerofthecircuit
byreducingtheflowofcurrentthroughthecircuit.
Thegoalofpowergatingistoswitchofftheentirecircuit
whennotinuse.

30. Clock gating
Thebasicideaofclockgatingistoreducethedynamicpower
consumptionofregistersbyswitchingoffunnecessaryclock
signalstotheregistersselectivelydependingonthecontrol
signalwithoutviolatingthefunctionalcorrectness.
Clockgatingmayleadtoaconsiderablepowerreductionofthe
overallsystemwithpropercontrolsignals.
Clockgatingsavespowerbypruningtheclocktree,atthecost
ofaddingmorelogictoacircuit.
Pruningtheclockdisablesportionsofthecircuitrysothat
theflip-flopsinthemdonothavetoswitchstates.
Switchingstatesconsumespower.Whennotbeingswitched,
theswitchingpowerconsumptiongoestozero,andonlyleakage
currentsareincurred.

31. Clock gating

32. Clockgatingistostoptheclockpulsetoaregisterwhennecessary.
Usuallytheassignmenttoaregistermightbeguardedwithsome
conditionasshowninFigure.
SoifENis0,wecanstoptheclocktoregisters.
Inthelogicsynthesis,thiskindofguardingassignmentis
manipulatedasfollows.
EnableconditiondefinedinFigureallowsregisterstoreceiveeither
newinputdataDATA_INwhenenablesignalENtakesvalue1,or
recycleddataDATA_OUTstoredintheregisterswhenENbecomes
0throughmultiplexers.
Foreachclockcycle,theregistershavetoswitchstates,which
dissipatepower.
Sincetheclocktreeconsumesupto45%ofthesystempower,
reductionofthisportionofpowercanleadtoaconsiderablepower
reductionofthewholecircuitdesign.
Clock gating

33. Power Gating for Leakage Power
Reduction
Powergatingisatechniquethatuses
sleeptransistorsashighthreshold
voltage(Vt)devicestodisconnectlow
Vtlogiccellsfromthesupplyorground
toreducetheleakageinthesleepmode
Powergatingcanbeimplementedin
fine-grainapproachandcoarse-grain
approachdependingonthenumberof
gatescontrolledbyonehighVtswitch
transistor.

34. Power Gating for Leakage Power
Reduction
Byfine-grainpowergatingapproach,asleeptransistorisaddedto
everycellandthepowerofeachclusterofcellsisgatedindividually.
Sincesleeptransistorsareinsertedintoeverycell,thisimposesalarge
areapenaltytotheoriginaldesign.
Thecoarse-grainstructureisageneralizationoftheso-called
MTCMOStechnique,whereaPMOSand/orNMOSsleeptransistoris
insertedintothesharedvirtualpowernetworksofCMOSgates.
ThesleeptransistorsarehighVtdevicesandareturnedoffwhenthe
gateisinstandbymode.
ThusthehighVtsleeptransistorswilldisconnectlowVtlogiccells
fromthesupplyand/orgroundtoreducetheleakagecurrent.
Keyquestionstoimplementsuchsleep/wake-upsignalsarehowto
reducethepowerconsumptionandthewake-uptimeduringthesleep-
activemodetransition.