about mos transistors AND THEIR CHARACTERSTICS

aBOUT WORKING OF NMOS AND PMOS TRANSISTORS

1. CMOS VLSI Design (10EC021) M.Tech (1 st Sem ) 2013 Batch --Prof. Nataraj Vijapur

2. Why to study CMOS VLSI?

3. Attributes of CMOS VLSI Logic Levels – Fully restored Equal transition times Memories—Low Power, High density Use of T.G., regular structures No static power consumption Easy Precharging capacity for nodes Power Supply-fixed % of VDD Layout –Regular & Easy automation

4. MOS Transistors Four terminal device: gate, source, drain, body Gate – oxide – body stack looks like a capacitor Gate and body are conductors (body is also called the substrate) SiO 2 (oxide) is a “good” insulator (separates the gate from the body Called metal–oxide–semiconductor (MOS) capacitor, even though gate is mostly made of poly-crystalline silicon (polysilicon) NMOS PMOS

5. NMOS Operation Body is commonly tied to ground (0 V) Drain is at a higher voltage than Source When the gate is at a low voltage: P-type body is at low voltage Source-body and drain-body “diodes” are OFF No current flows, transistor is OFF

6. NMOS Operation Cont. When the gate is at a high voltage: Positive charge on gate of MOS capacitor Negative charge is attracted to body under the gate Inverts a channel under gate to “n-type” (N-channel, hence called the NMOS) if the gate voltage is above a threshold voltage (VT) Now current can flow through “n-type” silicon from source through channel to drain, transistor is ON

7. PMOS Transistor Similar, but doping and voltages reversed Body tied to high voltage (V DD ) Drain is at a lower voltage than the Source Gate low: transistor ON Gate high: transistor OFF Bubble indicates inverted behavior

8. Power Supply Voltage GND = 0 V In 1980’s, V DD = 5V V DD has decreased in modern processes High V DD would damage modern tiny transistors Lower V DD saves power V DD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, ..

9. Transistors as Switches In Digital circuits, MOS transistors are electrically controlled switches Voltage at gate controls path from source to drain

10. 3: CMOS Transistor Theory 10 MOS Capacitor Gate and body form MOS capacitor Operating modes Accumulation Depletion Inversion Example with an NMOS capacitor

11. 3: CMOS Transistor Theory 11 Terminal Voltages Mode of operation depends on V g , V d , V s V gs = V g – V s V gd = V g – V d V ds = V d – V s = V gs - V gd Source and drain are symmetric diffusion terminals However, V ds  0 NMOS body is grounded. First assume source may be grounded or may be at a voltage above ground. Three regions of operation Cutoff Linear Saturation

12. 3: CMOS Transistor Theory 12 nMOS Cutoff Let us assume V s = V b No channel, if V gs = 0 I ds = 0

13. 3: CMOS Transistor Theory 13 NMOS Linear Channel forms if V gs > V t No Currernt if V ds = 0 Linear Region: If Vds > 0, Current flows from d to s ( e - from s to d) I ds increases linearly with V ds if V ds > V gs – V t . Similar to linear resistor

14. 3: CMOS Transistor Theory 14 NMOS Saturation Channel pinches off if V ds > V gs – V t . I ds “independent” of V ds , i.e., current saturates Similar to current source

15. 3: CMOS Transistor Theory 15 I-V Characteristics In Linear region, I ds depends on How much charge is in the channel How fast is the charge moving

16. 3: CMOS Transistor Theory 16 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate – oxide (dielectric) – channel Q channel =

17. 3: CMOS Transistor Theory 17 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate – oxide – channel Q channel = CV C =

18. 3: CMOS Transistor Theory 18 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate – oxide – channel Q channel = CV C = C g = e ox WL/t ox = C ox WL V = V gc – V t = (V gs – V ds /2) – V t C ox = e ox / t ox

19. 3: CMOS Transistor Theory 19 Carrier velocity Charge is carried by e- Carrier velocity v proportional to lateral E-field between source and drain v = m E m called mobility E = V ds /L Time for carrier to cross channel: t = L / v

20. 3: CMOS Transistor Theory 20 NMOS Linear I-V Now we know How much charge Q channel is in the channel How much time t each carrier takes to cross

21. 3: CMOS Transistor Theory 21 NMOS Saturation I-V If V gd < V t , channel pinches off near drain When V ds > V dsat = V gs – V t Now drain voltage no longer increases current

22. 3: CMOS Transistor Theory 22 NMOS I-V Summary Shockley 1 st order transistor models (valid for Large channel devices only)

23. Channel Length Modulation Reverse-biased p-n junctions form a depletion region Region between n and p with no carriers Width of depletion L d region grows with reverse bias L eff = L – L d Shorter L eff gives more current I ds increases with V ds Even in saturation

24. Chan Length Mod I-V  = channel length modulation coefficient not feature size Empirically fit to I-V characteristics

25. Body Effect V t : gate voltage necessary to invert channel Increases if source voltage increases because source is connected to the channel Increase in V t with V s is called the body effect

26. Body Effect Model  s = surface potential at threshold Depends on doping level N A And intrinsic carrier concentration n i  = body effect coefficient

27. OFF Transistor Behavior What about current in cutoff? Simulated results What differs? Current doesn’t go to 0 in cutoff

28. 28 PMOS I-V All dopings and voltages are inverted for PMOS Mobility m p is determined by holes Typically 2-3x lower than that of electrons m n Thus PMOS must be wider to provide same current In this class, assume m n / m p = 2 Body tied to high voltage (V DD ) Gate low: transistor ON Gate high: transistor OFF Bubble indicates inverted behavior

29. Inverter-?

30. CMOS Inverter

31. 32 Transistor Operation Current depends on region of transistor behavior For what V in and V out are nMOS and pMOS in Cutoff? Linear? Saturation?

32. I-V Characteristics

33. Graphical derivation of Inverter

34. 36 I-V Characteristics Make pMOS is wider than nMOS such that b n = b p

35. 4: DC and Transient Response 37 Current vs. V out , V in

36. Load Line Analysis For a given V in : Plot I dsn , I dsp vs. V out V out must be where |currents| are equal in values

37. 4: DC and Transient Response 39 Load Line Analysis V in = 0

38. 4: DC and Transient Response 40 Load Line Analysis V in = 0.2V DD

39. 4: DC and Transient Response 41 Load Line Analysis V in = 0.4V DD

40. 4: DC and Transient Response 42 Load Line Analysis V in = 0.6V DD

41. 4: DC and Transient Response 43 Load Line Analysis V in = 0.8V DD

42. 4: DC and Transient Response 44 Load Line Analysis V in = V DD

43. 4: DC and Transient Response 45 Load Line Summary

44. 46 DC Transfer Curve Transcribe points onto V in vs. V out plot

45. 4: DC and Transient Response 47 Operating Regions Revisit transistor operating regions Region nMOS pMOS A Cutoff Linear B Saturation Linear C Saturation Saturation D Linear Saturation E Linear Cutoff

46. Regions of operation…

47. Summary…

48. 4: DC and Transient Response 53 Beta Ratio If b p / b n  1, switching point will move from V DD /2

49. 54 Noise Margins How much noise can a gate input see before it does not recognize the input?

50. Noise-Margins.. LOW noise margin: is defined as the difference in magnitude between the maximum Low output voltage of the driving gate and the maximum input Low voltage recognized by the driven gate. HIGH noise margin: is defined difference in magnitude between minimum High output voltage of the driving gate and minimum input High voltage recognized by the receiving gate.

51. 4: DC and Transient Response 56 Logic Levels To maximize noise margins, select logic levels at unity gain point of DC transfer characteristic

52. 4: DC and Transient Response 57 Transient Response DC analysis tells us V out if V in is constant Transient analysis tells us V out (t) if V in (t) changes Requires solving differential equations Input is usually considered to be a step or ramp From 0 to V DD or vice versa

53. Static Load MOS Inverter

54. Static load nmos inverter… If R load increases, the VOL decreases (NML increases) and the “ ON”current decreases; If R load decreases, the VOL rises (NML decreases) and the “ ON”current rises. Resistors can be implemented using highly resistive undoped polysilicon . When transistors are used as a current-source load, the inverter is called a saturated load inverter if the load transistor is operated in saturation; if the load transistor is biased for use as a resistor, it is called an unsaturated inverter. The reason to use static load inverter is to reduce the number of transistors used for a gate to improve density and/or to lower dynamic power consumption

55. Pseudo NMOS Inverter Although pseudo- nMOS gates are not used for low power applications, they do find wide application in high-speed circuits and circuits that require large fan-in NOR gates

56. Pseudo NMOS…

57. More saturated load inverter

58. Depletion load inverter

59. CMOS inverter as an amplifier How to get maximum amplification? Bias at V inv using feedback resistor Use capacitor to AC couple the input

60. Transmission Gate Transmission gates find used as a multiplexing element, a logic structure, a latch element and an analog switch.

61. nMOS pass transistor

62. pMOS Pass transistor

63. Transmission gate characteristics

64. Overall Characteristics

65. Transmission Gate Characteristics

66. Transmission gate as a resistor

67. Tri-state Inverter

68. Inverter Cross-section Typically use p-type substrate for nMOS transistors Requires to make an n-well for body of pMOS transistors

69. Well and Substrate Taps Substrate must be tied to GND and n-well to V DD Metal to lightly-doped semiconductor forms poor connection called Schottky Diode Use heavily doped well and substrate contacts/taps (or ties)

70. Simplified Design Rules Conservative rules to get you started