Addressing Modes of 8051.pptx

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1. Module – 01/18EE52 Addressing Modes in 8051 MC Mr.V.Rajesh Kumar Course Instructor/EEE Dept Sir M Visvesvaraya Institute of Technology Bengaluru-56215 6 11/3/2022 Dept of EEE,Sir M Visvesvaraya Institute of Technology 1

2. A ddre s s i ng M ode M C 8051       Method of specifying the data to be operated by the instruction CPU can access the data in various ways. -- data could be in reg./Memory/immediate value. I s a w a y th e M C t o acces s d at a / op eran d f r om i n terna l m e m o r y / external memory (or)Register spe cific Ports .           Th e us e of e f f i c i en t m od e s of a p r og ra m ( a dd ress i n g m od e ) w i l l i ncreas e th e p r o cess i n g s p ee d of CP U a s we l l a s p r o cess i n g ti m e ca n be sh o rtene d. 11/3/2022 Dept of EEE,Sir M Visvesvaraya Institute of Technology 2

3. Types of Addressing Modes Register Addressing Mode Direct Addressing Mode Register indirect Addressing Mode Immediate Addressing Mode Indexed Addressing mode 11/3/2022 Dept of EEE,Sir M Visvesvaraya Institute of Technology 3

4. 1. Reg i st er A ddre ss i n g m ode    - Instruction will specify the name of the Reg. in which data is available This addre ssi ng i n s t ru c t io n i n volv es i nf o r m a ti o n tran s f er bet w e en reg is t ers ( at l ea s t o ne o f the R - R7 reg i s ter i n vo l v ed) Source & Destination reg.’s match in Size: Eg : MOV A, R0 MOV R2, A ADD A, R5 Eg : MOV R4, R5 (Invalid Instruction) Size of Source & Destination will vary: Eg : MOV DPTR, A (Error) MOV DPTR, #12A3H MOV R2, DPL MOV R1, DPH   11/3/2022 Dept of EEE,Sir M Visvesvaraya Institute of Technology 4

5. 1. Reg i st er A ddre ss i n g m ode      E x a m p l e : A DD A , R7 ; ad d co nt e nt o f A w i th the co n t e nt o f R7 M OV R , #0 ; mo v e da ta to t he r eg i s t e r R0 D J NZ R 3 , L O O P ; D ec r eme nt co n t e nt o f R3 a nd J u m p if N o t L OOP M OV R , A ; The i n s t r u c ti o n t r a n s f e r s the co nt e nt o f a c c u m ul a t o r A i nto the R0 r eg i s t e r . 11/3/2022 Dept of EEE,Sir M Visvesvaraya Institute of Technology 5

6. 2. D i r e c t A ddre ss i ng m ode       The Address of the data is directly specified in the instruction The entire 128 bytes of RAM can be accessed with memory locations 30H to 7FH Eg : Eg : M O V A, P 3 ; Tr an s f e r t he c on te n t s of P o r t 3 t o t he a cc umu l a t or M O V A, 020 H ; Tr an s f e r t he c on t e n t s o f RAM l o c a ti on 2 H t o t he a cc um u l a t or M O V P 1, A A H ; Tr an s f e r t he c on te n t s of A t o P o r t 1 M O V 2 H, 4 0H ; Tr a n s f e r t he c on te n t s of t he a d dr es s 4 H t o t he a ddr ess 2 H ADD A, 55 H ; A d d t h e c on te n t s of A wit h t he c on te n t s of t he a ddr es s 5 5 H MOV A, 7 OR MOV A, R7 (OR) MOV A, 7 MOV R0, 40H MOV R4, 7FH MOV 40H, A MOV R2, #5 R2=05H MOV B, 2 MOV 4, 2 (OR) MOV R4, R2 11/3/2022 Dept of EEE,Sir M Visvesvaraya Institute of Technology 6

7. Valid memory Address for Direct Addressing Mode P1(80H ), P1(90H ), P2(A0H), P3(B0H) & PSW(D0H ) PSW(D0H) Addressable memory used by direct addressing mode from 00 to 7F and also address specified by special register 11/3/2022 Dept of EEE,Sir M Visvesvaraya Institute of Technology 7

8. 3. Register I nd i re c t A ddre ss i ng m ode         A reg i st e r i s u s e d to h o l d the e ff e ct i ve addre s s o f t he oper a n d .       Th i s reg i st e r , w h i ch h o l d s t he add r e s s , i s c a ll e d t he Po in t e r reg i st e r a nd i s s a i d to p o i nt to t he opera n d .       O n l y reg i st e r s R0 , R 1 a nd D PTR c a n b e us e d a s po i n t e r reg i st er s.       R a nd R 1 r eg i st er s c a n h o l d a n 8 - b i t addre ss w h er e a s D PTR c a n h o l d a 16 - b i t addre s s.       D PTR i s u s e f ul i n a c c e s s i ng opera n d s w h i ch ar e i n t he e xt er n a l m e m or y. 11/3/2022 Dept of EEE,Sir M Visvesvaraya Institute of Technology 8

9. 3 . I nd i r e c t A dd r e ss i n g m od e ( c o n t’ d )   E x a m p l e s:     MO V @ R0 , A ; S t ore t he c on te nt of a cc u mu l a t o r i n t o t he m e mory l o c a t i on p o i n te d t o b y t he c on t e n t s of r e g i s t e r R0 . R c ou l d have an 8- b i t a d d r ess , s u c h as 6 H . MO V A , @ R ; move t he c on te n t s of RA M at l o c a t i o n d es i g na t e d b y R i n t o a cc umu l a t o r A    Eg : MOV P1, #0xFF H Let P1: 0000 0100b (OR) 04 H MOV A, P1 A = 04H MOV R0, # 050H R0 = 50 H MOV @R0, A Add. of Memory 0050 H = ------ MOV A, @R0 A = ---H 11/3/2022 Dept of EEE,Sir M Visvesvaraya Institute of Technology 9

10. MO V X A , @ D P T R ; T ran s f e r t he c on te n t s f rom t he m e mory l o c a t i o n p o i n te d t o b y DPT R i n t o t he a cc umu l a t or . D PT R c ou l d have a 1 6- b i t a dd r es s , s u c h as 1 23 4 H .      IN C @ R 1 a d d one i n t o t he c on te nt d es i g na t e d b y t he R 1 11/3/2022 Dept of EEE,Sir M Visvesvaraya Institute of Technology 10

11. MOV A, #55H A= 55h MOV R0, 40H R0 40H= ( xx ) MOV @R0, A 40H = --- H INC R0 R0 = 41 H MOV @R0, A 41 H = ---H INC R0 R0 = 42H MOV @R0,A 42H = ----H INC R0 R0 = 43H MOV @R0, A 43 H= ----H Example Advantages of reg. Indirect addressing Mode: Looping is most efficient & Block data transfer Limitations: need to access the external RAM 11/3/2022 Dept of EEE,Sir M Visvesvaraya Institute of Technology 11

12. 3 . I nd i r e c t A dd r e ss i n g m od e ( c o n t’ d ) 11/3/2022 Dept of EEE,Sir M Visvesvaraya Institute of Technology 12

13. 4. Im m ed i a t e A ddre s s i ng m ode         T h i s mo d e of a d dr es s i n g u se s e i t h e r an 8 - or 16 - b i t c on st ant v a l ue as t he s ou r c e o p er a n d T h i s c on st a n t i s s p e c i fi e d i n t he i n s t r u c t i on , r a t h e r t han i n a re g i st e r or a m e mo r y l o c a ti on T h e d es t i na t i on r e g i st e r s hou l d ho l d t he s a m e d a t a si z e w h ic h i s sp e ci fi e d b y t he s ou rc e o p e r and E x a m p l e s : ADD A , # 030 H ;A d d 8 - b i t v a l ue of 3 H t o t he a cc umu l a t or r e g i s t e r ( w h ic h i s an 8 - b i t r e g is t e r ). M O V D P T R , #0 F E H ; M o v e 1 6 - bi t d a t a c on st ant FE H i n t o t he 1 6 - b i t Da t a P o i n t e r Re g i s t e r . 11/3/2022 Dept of EEE,Sir M Visvesvaraya Institute of Technology 13

14. Examples: MOV A, # A0H ; data A0H transfer to the A ADD A, # 4EH ; add the contents of A with the data 4E H & store in Acc. A CJNE A, # 20H, LOOP ; compare the data 20H with content of Acc (A), jump to LOOP if the value not equal to zero. 4. Immediate Addressing mode (cont’d) 11/3/2022 Dept of EEE,Sir M Visvesvaraya Institute of Technology 14

15. 5. I nde x ed A d dre ss i n g m ode   On-Chip ROM access   T he I nde x ed addre ssi ng i s u s eful w h en there i s a need to retr i e v e data fr o m a loo k - up tab l e   A 1 6 - b i t reg is ter ( d ata p oi n t e r / pr o gram co unter – D P T R /PC ) h o l ds t h e ba s e addre s s and the a cc u m u l a t o r h ol ds an 8 - b i t d is p l a c e m e n t o r i ndex v a l u e     T he s u m o f the s e t w o reg is t ers f o r m s the effe c t iv e addre s s f o r a J M P o r M O V C i n s tru c t i o n 11/3/2022 Dept of EEE,Sir M Visvesvaraya Institute of Technology 15

16. I ndexe d A dd r e ss i n g mod e ( con t’ d ) E x a m p l e : M OV A, #08 H ; O f f se t f r o m t ab le s t a r t M OV D P TR , #01 F0 H ; T ab le s t a r t add re s s M O V C A , @ A + D P TR ; G e ts t a r ge t v a lue fr o m t he t ab le s t a r t add re s s + o ff se t a nd p uts it in A .   (Contents of A are added to the 16 bit reg. DPTR to form the 16 bit address of need data ) (A) { (A=00) + (Add. Of content) } A fter the e x e c ut io n o f the ab ov e i n s t r u c t i o n s , the pr o gram wi l l b ran c h to addre s s 1F 08 H ( 1 F 0H+ 08 H ) and tran s fer i nto the a cc u m u l a t o r the data b y te retr i e v ed fr o m that loc at i o n ( fr o m the look - u p t ab l e) 11/3/2022 Dept of EEE,Sir M Visvesvaraya Institute of Technology 16

17. ORG 0000 MOV DPTR, #200H CLR A MOVC A, @A+DPTR MOV R0,A INC DPTR CLR A MOVC A,@A+DPTR MOV R1, A INCR DPTR CLR A MOVC A,@A+DPTR MOV R2, A HERE: SJMP HERE ORG 0200H MY DATA: DB “ SLR” END. 11/3/2022 Dept of EEE,Sir M Visvesvaraya Institute of Technology 17

18. ORG 0000 MOV DPTR, #300H MOV A, #0FFH MOV P1, A BACK: MOV A, P1 MOVC A, @A+DPTR MOV P2 ,A SJMP BACK ORG 300H SQR_Table: DB 0, 1, 4, 9, 16, 25, 36, 49, 64, 81 END. MEMORY LOCATIONS IN ROM 307CONTENTS 300 00 301 01 302 04 303 09 304 10 Equivalent to 16 305 19 Equivalent to 25 306 24 Equivalent to 36 307 31 Equivalent to 49 308 40 Equivalent to 64 309 51 Equivalent to 81 Program to understand the concept of LOOK –UP table with INDEXED ADDRESSING MODE 11/3/2022 Dept of EEE,Sir M Visvesvaraya Institute of Technology 18

19. Thank You 11/3/2022 Dept of EEE,Sir M Visvesvaraya Institute of Technology 19