ADSP processor Notes by Pritish Vibhute.pptx

Advanced Digital System Processor design and development

1. 504107 Advanced DSP Processors

2. Subject Scheme Theory:- Teaching scheme :- 4Hrs/wk Examination scheme :- 50 Marks  InSem = 15 Marks Unit Test I 15 Marks Unit Test II 10 Marks Assignment I 10 Marks Assignment II 50 Marks  EndSem Credits : 4 Practical- ( shared between different subjects) Teaching scheme :- 2 Hrs/wk Examination scheme :- 50 Marks term work 10 Marks for each experiment converted to 5 50 Marks oral Credits : 4

3. Unit Test Pattern Based on first two Modules(1,2) Q1 or Q2 Q3 or Q4 Q5 Or Q6 Each Question 5 marks Total 15 marks Based on last two Module(3,4) Q1 or Q2 Q3 or Q4 Q5 Or Q6 Each Question 5 marks Total 15 marks Unit Test I Unit Test II

4. End-Semester Exam pattern Duration 3 Hrs Marks 50 Marks Solve any Five Questions[10 marks each] Q1 Q5 4 3 3 M I Q2 Q6 5 5 M II Q3 Q7 4 4 2 M III Q4 Q8 3 4 3 M IV

5. Syllabus Module I (8Hrs) Digital Signal Processor Architectures, hardware units as MAC unit, Barrel shifter, Address generators, pipelining, circular buffering, memory configurations, peripherals and input/output, Fixed point and floating point formats and digital signal processors, Concept of Real Time Processing. References :- Digital Signal Processor: SenM.Kuo , Woon-SengS.Gan , Pearson CH 1,3,4

6. BLOCK DIAGRAM OF DSP PROCESSOR

7. Multiply and accumulate It consists of adder, multiplier, accumulator. Entire process achieved in single clock cycle. Pipelined multiplier should be used for high output. Speed should be faster.

8. Arithmetic and logic unit It perform arithmetic and logical operations. It can operate with MAC and barrel shifters. The flags are used to indicate the status of result after ALU. It has fast double-precision capability. Association with shifters for scaling inputs.

9. Barrel shifter Direction left or right N bi input word Barrel Shifter N bit output word (shifter P bits ,left or right) P bit shift operator

10. Data address generators It includes data memory bus and program memory bus. DAGs keep a track of addresses of input data , coefficients stored in data & program memories. Types of registers are required for DAG: - Index register. - Modify register. - Length and base register.

11. Program sequences It generates instruction address. It selects the address of next instruction to be executed & manages execution of programs. DSP algorithms spend most of their time in loops.

12. Memory To increase the speed of operation, memories with low access time are required. The data memory is dual ported for simultaneous access by the DSP & IO Controller.

13. Syllabus Module II (8Hrs) Architecture of TMS320C54XX and TMS320C6713 , features, instruction sets , memory considerations, data types , addressing modes , various fields of application of the two processors. References :- Digital Signal Processor: SenM.Kuo , Woon-SengS.Gan , Pearson CH 4,5,6

14. Syllabus Module III (8Hrs) Embbeded processor: Micro Signal Architecture, Real time embedded signal processing, overview of Blackfin Processor, Hardware processing units and register files, Bus Architecture and memory, Basic peripherals, Introduction to VisualDSP ++, Software development flow and tools, linker files, debugging features. References :- Embedded Signal Processing with the Micro Signal Architecture: Woon-SengGan , Sen M. Kuo , Wiley publication CH 5

15. Syllabus Module IV (8Hrs) Selection criteria of Digital Signal Processor, sampling and quantization, coder-decoder, overview of C compiler, Assembler, linker, simulator, emulator. Code composer studio, creating, building of project, viewing memory and graphics, use of breakpoints. References :- Digital Signal Processor: SenM.Kuo , Woon-SengS.Gan , Pearson

16. Lab Practice II:- Practical Laboratory Experiments: (Any Two of Following) Write a program in C for Finite impulse response LPF or HPF or BPF filter and implement on TMS320C XXX processor. Write a program in C for infinite impulse response LPF or HPF or BPF filter and implement on TMS320C XXX processor. Write a program in C for Adaptive filter and implement on TMS 320C XXX processor. To implement coder-decoder using MATLAB Simulink .

17. Experiment I Design an implement an FIR low pass filter using TMS320c6713 DSK with following specifications: –cutoff frequency = 5 kHz –sampling frequency = 48 kHz –filter order = 40 –use Kaiser window with beta = 0.5

18. //Filter coefficients (in Q15 format) of FIR lowpass filter designed using Kaiser window with beta=0.5, //Cutoff frequency = 5kHz, Sampling frequency = 48 kHz, Filter order = 40. #define N 41 //length of filter short h[N]= { 245,-68,-390,-582,-543,-257,187,620,850,739, 266,-438,-1118,-1466,-1223,-271,1301,3208, 5034,6349,6827,6349,5034,3208,1301,-271, -1223,-1466,-1118,-438,266,739,850,620,187, -257,-543,-582,-390,-68,245}; // Implementation of FIR lowpass filter designed using Kaiser window with beta=0.5, //Cutoff frequency=5kHz, Sampling frequency = 48 kHz, Filter order = 40. #include "fir5000.cof" // coeff file #include "dsk6713_aic23.h“ //codec- dsk support file Uint32 fs =DSK6713_AIC23_FREQ_48KHZ; //set sampling rate int yn = 0; //initialize filter's output short x[N];

19. interrupt void c_int11() //ISR { short i ; x[0] = input_sample (); //newest input @ top of buffer yn = 0; //initialize filter output for (i = 0; i< N; i++) yn +=(h[i]*x[i]); //y(n) += h(LP#,i)*x(n-i) for ( i = N-1; i > 0; i --) //starting @ bottom of buffer x[i] = x[i-1]; //update input data output_sample ( yn >> 15); //output filter return; //return from interrupt } void main() { short i ; for ( i =0; i <N; i ++) { x[ i ] = 0; } //init buffer comm_intr (); //init DSK, codec, McBSP while(1); //infinite loop }

20. Experiment II Design an implement low pass elliptic IIR filter using TMS320c6713 DSK with MATLAB generated coefficients to meet following specifications: -sampling frequency = 16 kHz -Pass band = 0-3 kHz -transition width = 450 Hz -Pass band ripple = 0-5 dB -Stop band attenuation = 60 dB

21. #define stages 4 int b[stages][3]={ {32768, 50211, 32768}, {32768, 4823, 32768}, {32768, -12661, 32768}, {32768, -17746, 32768} }; int a[stages][2]={ {-40627,14944}, {-32814,22434}, {-26741,28524}, {-24488,31683} }; int sf [stages]={ 1894, 10427, 21412, 27401, }; // IIR.c IIR filter using cascaded Direct Form II //Coefficients a's and b's correspond to b's and a's from MATLAB #include "DSK6713_AIC23.h" //codec-DSK support file Uint32 fs =DSK6713_AIC23_FREQ_16KHZ; //set sampling rate #include "lpfiir.cof" short dly [stages][2] = {0}; //delay samples per stage

22. interrupt void c_int11() //ISR { short i , input; int wn , yn ; input = input_sample (); //input to 1st stage for ( i = 0; i < stages; i ++) //repeat for each stage { wn =input* sf [1]-((b[ i ][0]* dly [ i ][0])>>15) - ((b[ i ][1]* dly [ i ][1])>>15); yn=((a[i][0]*un)>>15)+((a[i][1]*dly[i][0])>>15)+((a[i][2]*dly[i][1])>>15); dly [ i ][1] = dly [ i ][0]; //update delays dly [ i ][0] = wn ; //update delays input = yn ; //intermediate output->input to next stage } output_sample ( yn >>15); //output final result for time n return; //return from ISR } void main() { comm_intr (); //init DSK, codec, McBSP while(1); //infinite loop }