Advantages of 64 Bit 5T SRAM

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International Journal of Scientific Research and Engineering Development-– Volume 2 Issue 6, Nov- Dec 2019
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RESEARCH ARTICLE OPEN ACCESS
Advantages of 64 Bit 5T SRAM
Supriya Raj *, Vishal Shrivastava**
*(Department of ECE, Global Engineering College, Jabalpur MP Email:
[email protected])
*(Department of ECE, Global Engineering College, Jabalpur MP Email: [email protected])

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Abstract:
It is seemed that we have to focus to minimize the power due to leakage current through a huge
number of transistors and the large memory substance. This dissertation gives 5 Transistors future SoC
(System on Chip) devices SRAM concept. Hence SRAM may be utilized in the place of 6 Transistors
SRAM. By using DSCH2 and Microwind 2.6K we are designing a layout of SRAM in 2.5µm and 1.5µm
technology by using 5 transistors and perform various operations on it. By using Microwind 2.6K software
we are designing a layout diagram and checked it through DRC rule checker and after that simulate the
layout and do the analysis. It helps to decrease the memory size.

Keywords — VLSI, SoC, SRAM, IC, DSCH2, DRC.
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I. INTRODUCTION

Power Dissipation contains static component and
dynamic component [5]. Static components of Power
Dissipation are very low and caused by leakage
current. Dynamic power or switching power is
mainly power dissipated when charging or
discharging capacitors. If the circuit isn’t in the
charge state and all the inputs are at some logic level
then Dynamic power consumption occurs. It
increases by the charging of output capacitance and
by the charging of output capacitance. Sometimes it
can significantly contribute to the entire power
consumption [6].

II. POWER DISSIPATION IN CMOS

There are 3 facts responsible for power
consumption-

i. Static power
ii. Dynamic power
iii. Short circuit power

PMOS device is ON and NMOS device is OFF (as
shown in figure) if the input is at logic 0 and gives
the output voltage logic 1 or VCC. Similarly NMOS
device is ON and PMOS device is OFF (as shown in
figure) if the input is at logic 1 and gives the output
voltage logic 0 or ground. By this study, we show
that in this logic input there is one transistor is always
in OFF condition. Hence because gate terminal has
no current flowing in it, the static power dissipation
is 0. Also between VCC to ground there is no any dc
path exist [8]. However, due to reverse-bias leakage
between diffused regions and the substrate, a small
amount of consumption is there.

III. SRAM DESIGN

Static random access memory is the basic building
block of CPU in a computer. In the IC all the
contents of different circuit are integrated in a single
chip. With the introduction of the integrated circuit,
microprocessor and all other devices was put in a
monolithic device which is called microcontroller. In
microcontroller all necessary components are built
together. Microcontroller also store data by using
SRAM. Microcontroller has basic registers, RAM,
memory and circuitry for control. Static Random
Access Memory (SRAM) is a type of Random
Access Memory in which the word static means the
date which is stored can be retained indefinitely,
without any demand for periodically refresh

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operation as long as a sufficient voltage is provided.
The traditional SRAM has six MOSFETs (2 PMOS
and 4 NMOS) to store a bit in the memory. This
system uses 2 CMOS Invertors, connecting back-to-
back and known as Storage Cell. 0 and 1 are the 2
stable states. NMOS-5 and NMOS-6 are controlled
from WL. NMOS-5 and NMOS-6 are known as
Access Transistors. (BL) ̅ and BL are the bit lines.
SRAM is faster than DRAM because its commercial
chips accept all address bits at a time. 2 strong ways
are used for saving leakage and active current. First,
lowering the operating voltage and secondly
reduction in the capacitance of bit line and word line.
Because by survey it is found that up to 70% power
is consumed due to bit lines discharging or charging
during reading and writing modes. [25].

IV. PROBLEM STATEMENT

Flow Chart for 5T bit SRAM


Fig. 1 Flow Chart for 5T SRAM


H. Mangalam and K.Gunavathi et al [2006, 7] this
paper shows that in the deep submicron regimes the
high leakage current may be majorly contribute to the
total power consumption in CMOS circuits as the
channel length, thickness of the gate oxide and
threshold voltage. This paper proposed an
Asymmetric SRAM (SA) cell with the extra
transistor that reduced the gate leakage as compared
to the conventional 6T SRAM cell. Further to reduce
the leakage an Adaptive voltage level was added that
controlled the effective voltage across SRAM cell in
the inactive mode.

Fig. 2 5T 1Bit SRAM (proposed)

Chetan Sharma et al [2011, 17] he was presented a
paper that gives low power at the different levels of
VLSI Designs and clock distribution methods. This
paper reviews different low power techniques at gate
level, architecture level and tradeoffs between
different clock distribution methods such as single
driver clock method and the distributed buffers clock
methods. He also observed various effects of
particular clock distribution method, such as clock
jitter and clock skew etc.

Both the invertors perform as the storage elements
whereas both the Access transistors perform the
communication with the BL. The access transistors
perform communication with the bit lines and the
invertors perform the storage element. Because by
survey it is found that up to 70% power is consumed
due to bit lines discharging or charging during
reading and writing modes. [25]. So that in proposed
work we are using only BL in SRAM and reduce one

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NMOS transistor. Therefore lower power is
consumed due to only one bit line discharging or
charging during reading and writing modes. But
challenge is this which Transistor should be
eliminated. Since Q is the desired output and it is
obtained by T5 so that T6 is the best choice. Now I
will describe the SRAM by using 5 Transistors. Here
I have proposed a 64 bits SRAM in 2.5µm
technology and 1.5µm technology and compare with
this by a conventional 1bit 6T SRAM and also
construct a 64 bit SRAM for 6T SRAM.

Firstly I have proposed 5 transistors SRAM cell for
one bit only in which leakage power reduce because
of the absent of the charging capacitor and the
discharging capacitor of one bit line (BL) ̅. Figure 5.2
shows the schematic of designing of 5 transistors
SRAM cell for one bit. Then in next state I am
selecting 0 for WL again. Hence SRAM is in write
state. In the proposed steps, we write 0→1. Now it is
reading 1. In the second step we write 1→0 and then
reading 0, whereas BL signal is controlled by the
pulse.

V. 64-BIT SRAM

Fig. 3 64-BIT 6 T SRAM

In this section I am giving the detailed simulation
analysis of the 64-bits SRAM. I am here also
estimating the effects on the power dissipation while
using my idea. I am designing schematic diagram of
the 5 transistors SRAM cell for 64 bits and then
implementing it by Microwind 2.6K. This designing
is based on the VLSI software of CMOS technology.
I will design the 5 transistors SRAM cell for 64 bits
and compare the result with the conventional 6
transistors SRAM cell for 64 bits. Transistors reduce
the dynamic power consumption during the writing
operation through proper discharging and charging of
bit line.

In 6 transistors SRAM cell, either BL or ̅©̅̅I̅ must
be discharged; hence during writing either 0 or 1 the
power consumption is more, whereas in the proposed
5 transistors SRAM cell I am presenting a single BL
from being discharge during the writing logic 1 and
logic 0.


Fig 4 Block diagram of 5T 64-bit SRAM

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Motoi Ichihashi, Youngtag Woo, Muhammed
Ahosan U Karim, Vivek Joshi and David Burnett et
al [2018, 1] compared to 6T SRAM, a larger number
of transistors are required for one cell resulting in
larger cell area. The 10T SRAM shows promising
performance improvement over the 8T cell with the
drawback of larger cell size.









Fig 5 Comparison of Cell area between different SRAM made by 6T SRSM

Let, take some area from the above work:
6T_HD=6T SRAM HD =1
6T_HC=6T SRAM HC =1.25
8T= 8T SRAM TP / 8T SRAM DP =2.13
10T_2_fin= 10T SRAM 2-fin =2.63
10T_3_fin = 10T SRAM 3-fin = 2.88
10T_4_fin = 10T SRAM 4-fin = 3.13

By applying the proposed methodology, in each of
the structures one Transistor is removed. It means
each of the area will be multiplied by 5/6.

6T_HD= 6T_HD x (5/6) =1 x (5/6) = 0.83
6T_HC= 6T_HC x (5/6) =1.25 x (5/6) = 1.0375
8T= 8T x (5/6) = 2.13 x (5/6) = 1.7679
10T_2_fin= 10T_2_fin x (5/6) =2.63 x (5/6) = 2.1829
10T_3_fin= 10T_3_fin x (5/6) = 2.88 x (5/6) = 2.3904
10T_4_fin= 10T_4_fin x (5/6) = 3.13 x (5/6) = 2.5979


Fig 6 Comparison of Cell area between different SRAM made by 5T SRSM


VI. 64-BIT SRAM

Fig 7 Layout Design of 64-Bit 5T SRAM Using 90nm Technology

Figure 7 shows Layout design of 64-bit 5T SRAM
by using 90nm technology. The 64-bit SRAM is
designed by using 1-bit SRAM in which all 1-bit
SRAM are arranged in row and column.

In this layout-
Power consumption is = 0.125*64 mW = 8 mW
Layout area is = (5362.5)gh
2*64 = 343200gh
2
No. of transistor = 6*64 = 384
Leakage currents tssEareirrrrrrrrrrErgJgoDrvrlprErDJm-pS–r

VII. CONCLUSION


Fig 8 Comparison between 64 BIT 6T and 5T SRAM

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In this work we conclude that we have implement
64 bit 5T SRAM which reduce 36.2% of power
dissipation in 2.5µm and 37.2% in 1.5µm
technologies over the 64 bit 6T SRAM. Also leakage
current reduction in 5T SRAM over the 6T SRAM is
tss(are)=35% and tss(are)=36.6% in 2.5µm and
1.5µm respectively. As well as area reduction in 5T
SRAM over the 6T SRAM is 30.2% in both 2.5µm
and 1.5µm.

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