AHB To APB BRIDGE.pptx

AHB to APB Bridge

1. AHB TO APB BRIDGE SAI CHARAN BEHARA

2. AHB (Advance High-performance Bus) Protocol: AMBA AHB is a bus interface suitable for high-performance synthesizable designs. It defines the interface between components, such as masters, interconnects, and slaves. AMBA AHB implements the features required for high-performance, high clock frequency systems including: • Burst transfers. • Single clock-edge operation. • Non-tristate implementation. • Wide data bus configurations, 64, 128, 256, 512, and 1024 bits.

3. Signal Source Description HCLK Clock Source All signal timings are related to rising edge of HCLK. Input signals are sampled on the rising edge of HCLK HRESETn Reset controller •Only active low signal •Resets the system and bus HRDATA Slave The read data bus transfers received data from the selected Slave to master HADDR Slave This is the AHB address bus. For this specification, the address width is fixed at 32. HPROT Slave Protection control signal, intended to implement some level of protection HSEL Slave Each Slave has its own select signal HSELx and this signal indicates that the current transfer is intended for the selected Slave. HSIZE Slave Indicates the size of the transfer. HMASTLOCK Slave •1 à Indicates current transfer is part of locked sequence (same timing as addr and control signal), if 0 unlocked transfer

4. Signal Source Description HRESP Multiplexer • After passing through the multiplexor, provides the master with additional information on the status of a transfer •When LOW, the HRESP signal indicates that the transfer status is OKAY When HIGH, the HRESP signal indicates that the transfer status is ERROR HTRANS Slave Indicates the transfer type. This can be: IDLE - Indicates that no data transfer is required. BUSY - Enables Master to insert idle cycles in the middle of a burst NONSEQUENTIAL - Indicates a single transfer or the first transfer of a burst (One in use). •SEQUENTIAL - The remaining transfers in a burst are SEQUENTIAL and the address is related to the previous transfer HREADYOUT Multiplexer When HIGH, the HREADYOUT signal indicates that a transfer has finished on the bus. This signal can be driven LOW to extend a transfer. HWDATA Slave Transfers data from the Master to Slave during write operations. Master holds the data until the transfer completes indicated by HREADY = 1 HWRITE Slave When HIGH this signal indicates a write transfer and when LOW a read transfer. HBURST[2:0] slave •Indicates if transfer is single transfer or forms burst of 4,8 and 16 beats or undefined length burts

5. APB (Advanced Peripheral Bus) Protocol : The Advanced Peripheral Bus (APB) is part of the Advanced Microcontroller Bus Architecture (AMBA) protocol family. It defines a low-cost interface that is optimized for minimal power consumption and reduced interface complexity. The APB protocol is not pipelined, use it to connect to low-bandwidth peripherals that do not require the high performance of the AXI protocol. The APB can interface with: AMBA Advanced High-performance Bus (AHB) AMBA Advanced High-performance Bus Lite (AHB-Lite) AMBA Advanced Extensible Interface (AXI) AMBA Advanced Extensible Interface Lite (AXI4-Lite)

6. Signal Source Description PCLK Clock Source Clock PADDR APB Bridge This is the APB address bus. It can be up to 32 bits wide and is driven by the peripheral bus bridge unit. PPROT APB Bridge To provide protection against illegal transactions. This signal indicates the Normal or privileged PPROT[0] , secure or non-secure PPROT[1] , Data or Instruction PPROT[2] PSEL APB Bridge The APB bridge unit generates this signal to each peripheral bus slave. It indicates that the slave device is selected and that a data transfer is required. PENABLE APB Bridge This signal indicates the second and subsequent cycles of an APB transfer. PWRITE APB Bridge This signal indicates an APB write access when HIGH and an APB read access when LOW.

7. Signal Source Description PWDATA APB Bridge This bus is driven by the peripheral bus bridge unit during write cycles when PWRITE is HIGH. This bus can be up to 32 bits wide PSTRB APB Bridge This signal indicates which byte lanes to update during a write transfer. There is one write strobe for each eight bits of the write data bus. PRDATA Slave Interface The selected slave drives this bus during read cycles when PWRITE is LOW. This bus can be up to 32-bits wide PSLVERR Slave Interface This signal indicates a transfer failure.

8. AHB TO APB BRIDGE It is required to bridge the communication gap between low bandwidth peripherals on APB with the high bandwidth ARM Processors and/or other high-speed devices on AHB. The AHB to APB bridge is an AHB slave known as an APB bridge, providing an interface between the high-speed AHB and the low-power APB. Read and write transfers on the AHB are converted into equivalent transfers on the APB. This ensures that there is no data loss between AHB to APB or APB to AHB data transfers. AHB2APB interfaces AHB and APB. It buffers address, controls and data from the AHB, drives the APB peripherals and return data along with response signal to the AHB. The AHB2APB interface is designed to operate when AHB and APB clocks have the any combination of frequency and phase. The AHB2APB performs transfer of data from AHB to APB for write cycle and APB to AHB for Read cycle.

9. UVM ARCHITECIURE

10. TOP Test ENV SCOREBOARD AGENT DRIVER SEQUENCER MONITOR DUT INTERFACE

11. In a DUT and it will interact with it in order to test its functionality, so we need to stimulate it. To achieve this, a block that generates sequences of bits to be transmitted to the DUT, this block is going to be named  sequencer . Usually sequencers are unaware of the communication bus, they are responsible for generating generic sequences of data and they pass that data to another block that takes care of the communication with the DUT. This block will be the  driver . While the driver maintains activity with the DUT by feeding it data generated from the sequencers, it doesn’t do any validation of the responses to the stimuli. We need another block that listens to the communication between the driver and the DUT and evaluates the responses from the DUT. This block is the  monitor . Monitors sample the inputs and the outputs of the DUT, they try to make a prediction of the expected result and send the prediction and result of the DUT to another block, the  scoreboard , in order to be compared and evaluated.

12. TOP Test sequence sequence Environment AHB Agent APB Agent Scoreboard driver sequencer monitor sequencer driver monitor Virtual interface Virtual interface Virtual interface Virtual interface Interface Interface DUT

13. Read Transfer

14. Write Transfer

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