Arm modes

This presentation aims to provide information regarding all seven operational modes of the arm processor except the monitor mode.

1. By : Abhishek Pande 13BEI0004 Submitted to: Prof. V Ramesh ARM Processor Modes

2. Introduction Processor modes  refer to the various ways that the  processor  creates an operating environment for itself. Specifically, the processor mode   controls how the processor sees and manages the system memory and the tasks that use it . In the old days, you had a processor and it executed instructions. When an interrupt occured, the processor would save its current state and then branch to a specific place in order to service the interrupt. Thus, essentially, the processor had just two 'modes' - dealing with an interrupt, and not . But now the processors are much more capable and provide us with the option of multitasking and desired level of privilege.

3. Overview of Modes ARM processors support different processor modes, depending on the architecture version:- Processor mode Architectures Mode number User All 0b10000 FIQ - Fast Interrupt Request All 0b10001 IRQ - Interrupt Request All 0b10010 Supervisor All 0b10011 Abort All 0b10111 Undefined All 0b11011 System ARMv4 and above 0b11111 Monitor Security Extensions only 0b10110

4. Overview cont... User mode: It is the usual ARM program execution state, and is used for executing most application programs . Fast Interrupt  (FIQ ): This mode supports a data transfer or channel process . Interrupt  (IRQ) mode is used for general-purpose interrupt handling . Supervisor mode is a protected mode for the operating system . Abort mode is entered after a data or instruction Prefetch Abort.

5. Overview cont... System mode is a privileged user mode for the operating system . Undefined mode is entered when an undefined instruction is executed . Mode Mode identifier User usr Fast interrupt fiq Interrupt irq Supervisor svc Abort abt System sys Undefined und Table  :  Register mode identifiers

6. Register Organisation Summary

7. User Mode It is the unprivileged mode under which most tasks run. Unprivileged mode means that it doesn’t have access to the full system resources and cannot change the mode freely. It has access to the base register set i.e. at any time all the 16 registers from R0 to R15(pc) can be accessed. CPSR (Current Program Status Register) is a 32-bit wide register used in the ARM architecture to record various pieces of information and flags regarding the state of the program being executed by the processor and the state of the processor . This register’s values can be read from the User mode.

8. Every processor mode except user mode can change mode by writing directly to the mode bits of the CPSR. A banked register maps one-to-one onto a user mode register. SPSR (Saved Program Status Register) is not available in this mode. User Mode Cont…

9. System Mode It is a privileged mode unlike the User mode but uses the same set of registers as the User mode. All regular application tasks can be performed in this mode. Also all the files except the kernel files can be accessed through this mode. Both R/W is possible. We can only enter System mode from another privileged mode by modifying the mode bit of the  Current Program Status Register  (CPSR ) and it cannot be entered by an exception. System mode doesn’t have a set of associated banked registers which all the other privileged modes have.

10. A problem with the original design of the ARM is that as processor vectors modify R14 with the return address, an exception handler (for example,  IRQ ) that calls subroutines  cannot  act in a re-entrant way; for if the IRQ handler is taken while  in  the IRQ handler and having called a subroutine to handle the (first) IRQ, the return address in R14 will be trashed by the second IRQ exception . Ways around this involve clever coding to avoid an exception of the same type occurring, or to avoid taking subroutine calls, or switching to USR mode. Or in the case of interrupts, disabling them completely during the interrupt process. System Mode Cont…

11. But as of ARMv4, an alternative is proposed viz. the   System mode . It is like a cross between SVC and USR. System mode offers the privileges of SVC mode, however it uses the USR registers . An exception handler can safely deal with R14 and CPSR and so re-entrancy is possible. This deals with the corruption of the link registers. System Mode Cont…

12. Supervisor Mode This is a privileged mode which can be entered by pressing RESET when a software interrupt instruction is executed. Being in this mode we can breach the kernel files. Updating these kernel files and even modifying them is also possible but the warranty of the OS is rendered void if it’s done. For e.g: Modifying the kernel files to install a new OS in devices such as cell phones is done by entering into this mode. This process is more popularly called “rooting” for Android OS wherein we can access various privileged Android subsystem files. For iOS it’s called “jailbreaking”.

13. It’s basically a protected mode for the Operating System which is uniquely reserved for it. In this mode R13(sp), R14(lr) and CPSR registers are banked. OS calls the SWI to enter into SVC mode and then processor jumps to &FFFF0008 location. After subsystem reset, the ARM begins processing at address &FFFF0000(for high vector config.) viz. the reset vector address with interrupts disabled. To handle the problem of link register corruption, Linux kernel does it this way: whenever any interrupt occurs in the first level IRQ handler, it copies IRQ registers to SVC registers and switches the ARM to SVC mode. Supervisor Mode Cont…

14. When power is supplied to the core, it starts in the SVC mode. A Software Interrupt (SWI) exception occurs when the SWI instruction is executed and none of the other higher-priority exceptions have been flagged. On entry to the handler, the CPSR will be automatically set to the supervisor mode. Supervisor Mode Cont…

15. FIQ Mode FIQ or Fast Interrupt mode is a privileged mode which can be entered when a high priority interrupt is raised. This mode is useful for digital data processors that have the ability to handle multiple interrupts. When a fast interrupt request is received a flag is set and the program counter(pc or R15) and condition code registers are stored on a stack .  FIQ is just a higher priority interrupt request, that is prioritized by disabling IRQ and other FIQ handlers during request servicing. Therefore, no other interrupts can occur during the processing of the active FIQ interrupt.

16.  At the end of the ISR the return from interrupt instructions retrieves the condition code register which contains the status of the digital data processor and checks to see whether the flag has been set or not. If the flag is set it indicates that a fast interrupt was serviced and therefore only the program counter(R15) is unstacked . It is based on the same concept of a two-level interrupt system where a more important interrupt can interrupt an interrupt ! FIQ mode provides a large number of banked registers (R8 to R14, CPSR) and is useful for things that must complete extremely quickly or else data loss is a possibility. FIQ Mode Cont…

17. The original (8MHz) ARM used FIQ for networking and floppy disc which  had  to be serviced as soon as data was available. Modern ARMs would probably use FIQ for high speed DMA-style transfers . CPSR bit 6/F controls the masking of FIQ. FIQ vectors are similar to IRQ vectors but they are reserved for hardware requiring faster response times. FIQ Mode Cont…

18. IRQ Mode IRQ or Interrupt mode is a privileged mode which can be entered when a low priority interrupt is raised. This is the other, regular, interrupt mode. Only R13, R14, and CPSR registers are banked. Since IRQ has a lower priority than FIQ . This means that when the core takes an FIQ exception, it automatically masks out IRQs. An IRQ cannot interrupt the FIQ handler .  All interrupts that don't require extreme speed (clock ticks, screen VSync, keyboard, etc...) will use IRQ mode.

19. W hen the processor is in the IRQ mode, the instructions you execute still access registers R13 and R14. However, these registers are the banked registers r13_irq and r14_irq. The user mode registers r13_usr and r14_usr are not affected by the instructions referencing these registers. The program still has normal access to other registers R0 to R12. The following figure shows mode change from User to IRQ when an interrupt request occurs due to an external device raising interrupt to the processor core. This change causes user registers R13 and R14 to be banked. The user registers are replaced with registers r13_irq and r14_irq, respectively. Note r14_irq contains the return address and r13_irq contains the stack pointer for interrupt request mode. IRQ Mode Cont…

20. IRQ Mode Cont…

21. The fig also shows a new register appearing in interrupt request mode: the Saved Program Status Register (SPSR), which stores the previous mode’s CPSR. You can see in the diagram the cpsr being copied into spsr_irq. CPSR bit 7/I controls the IRQ masking. So why do many systems use IRQ and not FIQ? It’s because all of the interrupt controller hardware is typically on the IRQ pin and using FIQ only makes sense if you have a single highest priority interrupt source connected to the nFIQ input and many systems do not have a single permanent highest priority source. IRQ Mode Cont…

22. Abort Mode This privileged mode is used to handle memory access violations. An abort is signalled by the memory system as a result of a failure to load either an instruction (Prefetch Abort) or data (Data abort ). A  Prefetch Abort  occurs if the processor attempts to  execute  a failed instruction load (note - no abort happens if the processor fails to load an instruction, but said instruction is  not  executed due to a branch or suchlike). In ARMv5 a Prefetch Abort can be generated programatically by the use of the  breakpoint  instruction.

23. A  Data Abort  occurs if the processor attempts to fetch data but the memory system says it is unable to due to incorrect access permissions. The abort occurs before the failed instruction alters the processor state. In both cases, interrupts are disabled and the branch is taken. When we acess data through protected memory, we can go into Abort mode. We can reserve any amount of data in protected memory but it’s in ‘read only’ form so if a user tries to write data into the protected memory, the system goes into Abort mode. Abort Mode Cont…

24. It’s not a working mode as such but a warning mode which if triggered, the processor cannot perform any other task. In general, a processor enters abort mode when there is a failed attempt to access memory. This mode has R13, R14 and SPSR as banked registers. It’s underlying mechanism is that whenever an abort signal is routed to the processor core, it responds to this signal by taking an exception and vectoring to the abort handler. The abort handler then determines the abort type as either a prefetch or a data abort, and based on the abort type the handler branches to the appropriate service routine. Abort Mode Cont…

25. Undefined Mode It’s a privileged mode and not a working mode as such. It’s also an error mode. When the processor tries to execute an invalid or undefined instruction, it automatically goes to the undefined mode. An Undefined instruction vector is used when the processor cannot decode an instruction. Since this is an ARM exception so instead of loading regular instructions, some special instructions are loaded from the exception vector table. Each vector table entry contains a form of branch instruction pointing to the start of a specific routine.

26. When an undefined instruction is encountered, the ARM will wait for a coprocessor to acknowledge that it can deal with the instruction (if in co-processor instruction space). If no coprocessor responds, or the instruction is one that is not defined, then the undefined instruction vector is taken. This will branch to & FFFF0004 address to allow such things as software emulation of coprocessors, or other extensions to the instruction set . An Undefined Instruction exception occurs when an instruction not in the ARM or Thumb instruction set reaches the execute stage of the pipeline and none of the other exceptions have been flagged. Undefined Mode Cont…

27. Since coprocessors follow the pipeline, instruction identification can take place in the execute stage of the core. If none of the coprocessors claims the instruction, an Undefined Instruction exception is raised. Both the SWI instruction and Undefined instruction have the same level of priority. If this mode is triggered, then the processing is stalled like the Abort mode. Undefined Mode Cont…

28. Why Do We Need So Many Modes? Unlike the yesteryears processors, today’s competetive market requires higher level of functionality and much greater freedom to the developer or even the end user to use a system in his/her on personalised manner. Multitasking or the ability to run various programs at the same time is of great importance today. Moreover these multiple modes provide some banked registers. These extra registers allow us to write much less complicated exception routines. Without them the function return address in LR register would blow up everytime an interrupt taken!

29. With these extra registers at our disposal, we have the option of not having to save and restore more processor context in software which in turn speeds up the interrupt handling process. Furthermore, with such high level of complexity in the instuction set used, it should be made sure that none  of the mere programs should be able to mess around with the OS or the machine's hardware. This is managed , in part , by the use of an MMU or other memory management system, and in part by the use of privilege . It is the various processor modes that provide the desired level of privilege . Cont…

30. THE END Thank You!