ARM Versions, architecture

UNIT 2 -ARM INTRODUCTION

1. EMBEDDED AND REAL TIME SYSTEMS

2. 3 MODES OF OPERATION ARM THUMB JAZELLE 2 ARM instruction set – instructions are all 32 bits long Thumb instruction set – instructions are a mix of 16 and 32 bits ( THUMB 2 ) Jazelle -DBX - provides acceleration for Java VM Jazelle -RCT - provides support for interpreted languages

3. ARM ARCHITECTURE VERSIONS 3

4. ARM ARCHITECTURE VERSIONS 4

5. ARM ARCHITECTURE VERSIONS 5

6. ARM ARCHITECTURE VERSIONS 6

7. Architecture ARMv7 profiles Application profile (ARMv7-A ) Memory management support Highest performance at low power To run applications/OS system requirements. TrustZone and Jazelle -RCT for a safe, extensible system e.g. Cortex-A5, Cortex-A9 RTA : SmartPhones , Digital TV, Servers & Networking Real-time profile (ARMv7-R) Protected memory (MPU) Low latency predictability ‘real-time’ needs e.g. Cortex-R4 high-performance, real-time, safe, and cost-effective RTA: Automobiles (ABS), Cameras, Disk drive controllers Microcontroller profile (ARMv7-M, ARMv7E-M) Lowest gate count entry point Deterministic and predictable behavior a key priority e.g. Cortex-M3 RTA: Low Cost MC, Mixed signal devices, Data communication 7

8. ARM ARCHITECTURE VERSIONS ARM V8 It adds a 64-bit architecture 64-bit general purpose registers, SP (stack pointer) and PC (program counter) The execution states support three key instruction sets: A32 (or ARM) : a 32-bit fixed length instruction set T32 (Thumb) introduced as a 16-bit fixed-length instruction set A64 is a 64-bit fixed-length instruction 8

9. What is the key feature? PIPELINE 9

10. 10 ARM 7 Vs 9

11. ARM 10 Vs 11 11

12. ARM NOMENCLATURE ARMxyzTDMIEJFS 12 – X: series – y: MMU – z: cache – T: Thumb – D: debugger – M: Multiplier (MAC) – I: Embedded ICE (built-in debugger hardware) – E: Enhanced instruction – J: Jazelle (JVM) – F: Floating-point – S: Synthesizible version (source code version for EDA Tools)

13. Embedded Processors

14. Application Processors

15. Development of the ARM Architecture 2

16. 16

17. INTRODUCTIONTO ARM 3

18. 32-bit load / store RISC architecture The only memory accesses allowed are loads and stores Most internal registers are 32 bits wide Most instructions execute in a single cycle 18

19. Byte means 8bits Halfword means 16 bits (two bytes) Word means 32 bits (four bytes) Doubleword means 64 bits (eight bytes) . TERMS 19

20. REGISTERS OF ARM Data registers: r0 to r12 SFR: r13, r14 & r15 Two status registers: CPSR: Current Program Status Register SPSR: Saved Program Status Register 20

21. 7 PROCESSOR MODES 21

22. The ARM Register Set r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r15 (pc) cpsr r13 (sp) r14 (lr) User mode spsr r13 (sp) r14 (lr) IRQ FIQ r8 r9 r10 r11 r12 r13 (sp) r14 (lr) spsr spsr r13 (sp) r14 (lr) Undef spsr r13 (sp) r14 (lr) Abort spsr r13 (sp) r14 (lr) SVC Current mode Banked out registers ARM has 37 registers, all 32-bits long A subset of these registers is accessible in each mode Note: System mode uses the User mode register set.

23. Data alignment

24. LSB ADDRESS 00 24

25. Program Status Registers 25 BITS (0-7 ) C –CONTROL, BITS (8-15) X- EXTENSION BITS (16-23) S - STATUS, BITS (24-31) F-FLAGS

26. ARM MEMORY ORGANIZATION

27. 27 Thanks!