AVR FAMILY OVERVIEW Mega AVR Program memory: 4K-256K Package:28-100 pins Extensive peripheral set, extended instruction set.
AVR FAMILY OVERVIEW Tiny AVR Program memory: 1K-8K Package:8-28 pins limited peripheral set and instruction set.
AVR FAMILY OVERVIEW Special purpose AVR
GPRs in the AVR
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AVR Data Memory GPRs- 2B IO Registers- 64B SRAM-(128 B to 4KB)
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Using instructions with the Data Memory LDS ( L oa D direct from Data S pace): LDS Rd, K
STS( ST ore direct to data S pace): STS K, Rr
AVR STATUS REGISTER
AVR DATA FORMAT AND DIRECTIVES Data format Representation : Hex Numbers Decimal numbers Binary numbers ASCII characters
Assembler Directives .EQU .ORG .INCLUDE Segment` Directive Description Header .DEVICE Defines the type of the target processor and the applicable set of instructions (illegal instructions for that type trigger an error message, syntax: .DEVICE AT90S8515) .DEF Defines a synonym for a register (e.g. .DEF MyReg = R16) .EQU Defines a symbol and sets its value (later changes of this value remain possible, syntax: .EQU test = 1234567, internal storage of the value is 4-byte- Integer) .SET Fixes the value of a symbole (later redefinition is not possible) .INCLUDE Includes a file and assembles its content, just like its content would be part of the calling file (typical e.g. including the header file: .INCLUDE "C:\avrtools\appnotes\8515def.inc") Code .DB Inserts one or more constant bytes in the code segment (could be numbers from 0..255, an ASCII-character like 'c', a string like ' abcde ' or a combination like 1,2,3,'abc'. The number of inserted bytes must be even, otherwise an additional zero byte will be inserted by the assembler.) .DW Insert a binary word in the code segment (e.g. produces a table within the code) .LISTMAC Macros will be listed in the .LST-file. (Default is that macros are not listed) .MACRO Beginning of a macro (no code will be produced, call of the macro later produces code, syntax: .MACRO macroname parameters, calling by: macroname parameters) .ENDMACRO End of the macro Everywhere .ORG Defines the address within the respective segment, where the assembler assembles to (e.g. .ORG 0x0000) .EXIT End of the assembler-source code (stops the assembling process)
Structure OF AVR Assembly Language
Assembling AVR program
PROGRAM COUNTER(PC) IN AVR Program Counter & Program ROM space in the AVR: Address of the next instruction to be executed. As the CPU fetches the opcode from program ROM, the PC is incremented by 1, which points to the next instruction. Size of PC—(14 bit to 22-bit). In AVR microcontrollers, each flash memory location is 2-bytes wide. e.g. ATMega32---> ROM size is 32KB organized as 16KB x 2B.
ROM memory map in AVR family
Placing code in program ROM
ROM width in the AVR AVR is word-addressable.
Harvard Architecture in the AVR Harvard Architecture in the AVR:
Instruction size of the AVR
ADD INSTUCTION FORMATION
FEATURES RISC processors have a fixed instruction size. RISC processors have a large number of registers. RISC processors have small instruction set. >95% instructions are executed with only single clock cycle. RISC processors have separate buses for program and data. In RISC, there are 4 sets of buses- 1) a set of data buses for carrying data (operands) in and out of CPU. 2) a set of address buses for accessing the data. 3) a set of buses to carry the opcodes. 4) a set of address buses to access the opcodes.
FEATURES 5.RISC uses LOAD/STORE architecture. 6. RISC instructions are implemented using hardwire method. Hardwiring of RISC instructions takes no more than 10% of the transistors.