Binary Adders.pdf

It is binary adder for engineer.

1. Binary Adder and Subtractor
Department of Electronics and Communication Engineering,
National Engineering College,
Kovilpatti

2. Table of contents
Binary Adder
Half Adder
Full Adder
Binary Subtractor
Half Subtractor
Full Subtractor
Parallel Adders
Carry Look Ahead Adder
BCD Adder
Problems

3. Half Adder
Figure:
IA combination circuit that performs addition of two bits
IConsists of two inputs - Augend (A) and Addend (B) and two
outputs - Sum (S) and Carry (C)

4. Half Adder Truth Table
Figure:
The corresponding Boolean expressions for Sum and Carry are,
S=AB+AB
=AB
C=AB

5. Half Adder Logic Circuit
Figure:
S=AB
C=AB

6. Full Adder
Figure:
IA combination circuit that performs addition of three bits
IConsists of three inputs - Augend (A), Addend (B) and
Carry-in (Cin) and two outputs - Sum (S) and Carry-out (Cout)
IThe termfull adderindicates that it can be implemented
usingtwo half adders

7. Full Adder Truth Table
Figure:

8. Simplied expression for Sum andCarryout
Figure:
The corresponding Boolean expressions for Sum and Carry-in are obtained as
S=ABCin+ABCin+ABCin+ABCin
=Cin(AB+AB) +Cin(AB+AB)
=Cin(AB) +Cin(AB)
=CinAB
Cout=AB+BCin+ACin
=AB+BCin(A+A) +ACin(B+B)
=AB+ABCin+ABCin+ABCin+ABCin
=AB(1 +Cin) +Cin(AB+AB)
=AB+Cin(AB)

9. Full Adder Logic Circuit
Figure:
S=ABCin
Cout=AB+Cin(AB)

10. Full Adder Using Two Half Adders
Figure:

11. Half Subtractor
Figure:
IA combination circuit that performs subtraction of two bits
IConsists of two inputs - Minuend (A) and Subtrahend (B) and
two outputs - Dierence and Borrow

12. Half Subtractor Truth Table
Figure:
The corresponding Boolean expressions for Dierence and Borrow
are,
Dierence=AB+AB
=AB
Borrow=AB

13. Half Subtractor Logic Circuit
Figure:
Dierence=AB
Borrow=AB

14. Full Subtractor
Figure:
IA combination circuit that performs addition of three bits
IConsists of three inputs - Minuend (A), Subtrahend (B) and
Borrow-in (Bin) and two outputs - Dierence (D) and
Borrow-out (Bout)

15. Full Subtractor
Consider the example, (010)2- (001)2

16. Full Subtractor Truth Table
Figure:

17. Simplied expression for Dierence andBorrowout
Figure: Borrowout
The corresponding Boolean expressions for Dierence andBorrowoutare obtained as
D=ABBin+ABBin+ABBin+ABBin
=Bin(AB+AB) +Bin(AB+AC)
=Bin(AB) +Bin(AB)
=BinAB
Bout=AB+ABin+BBin
=AB+ABin(B+B) +BBin(A+A)
=AB+ABBin+ABBin+ABBin+ABBin
=AB(1 +Bin) +Bin(AB+AB)
=AB+Bin(AB)

18. Full Subtractor Logic Circuit
Figure:
Dierence=ABCin
Bout=AB+Bin(AB)

19. Parallel Adder
Figure:
IOne full adder adds two bits and one carry. So for addingn
bits, we requirenfull adders
IAnbit parallel adder consists ofnfull adders connection in a
chain for adding two n bit sequences
IThe output carry from each full adder is given as carry input
to the next consecutive full adder and so on.

20. Carry Look Ahead Adder
Figure:
IEach full adder waits for the carry resulting from the addition of
previous bits
Ii
th
full adder waits for (i1)
th
full adder to generate the carry-out
ISo there is a considerable delay which is known as carry propagation
delay
ITo reduce this carry propagation delay,Carry Look Ahead Logicis
implemented

21. Carry Look Ahead Adder
Figure: PiandGi
Pi=AiBi
Gi=AiBi
The output sum and carry can be expressed as
Si=PiCi
Ci+1=Gi+PiCi

22. Carry Look Ahead Adder
IGiisCarry Generateand it produces a carry of 1 if bothAi
andBiare 1, regardless ofCi
IPiisCarry Propagate, because it determines whether a carry
fromstageiwill propagate tostagei+1
IBoolean function for each output carry is given as
C0=inputcarry
C1=G0+P0C0
C2=G1+P1C1
=G1+P1(G0+P0C0)
=G1+P1G0+P1P0C0
C3=G2+P2C2
=G2+P2(G1+P1G0+P1P0C0)
=G2+P2G1+P2P1G0+P2P1P0C0

23. Carry Look Ahead Adder
IHereC3need not wait forC2
IThus gain in speed is obtained at the expense of additional
hardware
Figure:

24. Carry Look Ahead Adder
Figure:

25. Derivation of BCD Adder
Figure:

26. Derivation of BCD Adder
IWhen the binary sum exceeds 1001, 0110 is added to make it
a valid BCD sum
IFrom the table, it is observed that correction is added when
i
ii Z8and eitherZ4&Z2
C=K+Z8Z4+Z8Z2
ISo, if C = 1, 0110 is added to the sum.

27. Derivation of BCD Adder
Figure:

28. Problem 1
[GATE-CS-2015] A half adder is implemented with XOR and AND
gates. A full adder is implemented with two half adders and one
OR gate. The propagation delay of an XOR gate is twice that of
an AND/OR gate. The propagation delay of an AND/OR gate is
1.2 microseconds. A 4-bit ripple-carry binary adder is implemented
by using full adders. The total propagation time of this 4-bit
binary adder in microseconds is

29. Problem 1
[GATE-CS-2015] A half adder is implemented with XOR and AND
gates. A full adder is implemented with two half adders and one
OR gate. The propagation delay of an XOR gate is twice that of
an AND/OR gate. The propagation delay of an AND/OR gate is
1.2 microseconds. A 4-bit ripple-carry binary adder is implemented
by using full adders. The total propagation time of this 4-bit
binary adder in microseconds is

30. Solution GATE-CS-2015
IFull adder consists of 2 XOR, 2 AND and 1 OR gates
IThe worst case propagation delay is then,
i
C1).
ii
iii
carry-out outputs (Cn-1 Cn and Sn-1).
IHence the total propagation delay for a n-bit full adder is,
tp= 4 + 2(n2) + 2
= 2n+ 2

31. Solution GATE-CS-2015
A half adder is implemented with XOR and AND gates. A full
adder is implemented with two half adders and one OR gate. The
propagation delay of an XOR gate is twice that of an AND/OR
gate. The propagation delay of an AND/OR gate is 1.2
microseconds. A 4-bit ripple-carry binary adder is implemented by
using full adders. The total propagation time of this 4-bit binary
adder in microseconds is
Answer: 4[(2n+2)*1.2] = 19.2ms

32. Solution GATE-CS-2015
A half adder is implemented with XOR and AND gates. A full
adder is implemented with two half adders and one OR gate. The
propagation delay of an XOR gate is twice that of an AND/OR
gate. The propagation delay of an AND/OR gate is 1.2
microseconds. A 4-bit ripple-carry binary adder is implemented by
using full adders. The total propagation time of this 4-bit binary
adder in microseconds is
Answer: 4[(2n+2)*1.2] = 19.2ms

33. Problem 2
[GATE-EC-2017] Figure I shows a 4-bit ripple carry adder realized using
full adders and Figure II shows the circuit of a full-adder (FA). The
propagation delay of the XOR, AND and OR gates in Figure II are 20 ns,
15 ns and 10 ns, respectively. Assume all the inputs to the 4-bit adder
are initially reset to 0.
At t = 0, the input to the 4-bit adder are changed toA3A2A1A0= 1100,
B3B2B1B0= 0100 andC0= 1. The output of the ripple carry adder will
be stable at t (in ns)=
Solution:
Link

34. Problem 2
[GATE-EC-2017] Figure I shows a 4-bit ripple carry adder realized using
full adders and Figure II shows the circuit of a full-adder (FA). The
propagation delay of the XOR, AND and OR gates in Figure II are 20 ns,
15 ns and 10 ns, respectively. Assume all the inputs to the 4-bit adder
are initially reset to 0.
At t = 0, the input to the 4-bit adder are changed toA3A2A1A0= 1100,
B3B2B1B0= 0100 andC0= 1. The output of the ripple carry adder will
be stable at t (in ns)=
Solution:
Link

35. Problem 3
[GATE ECE 2014 Set 4] A 16-bit ripple carry adder is realized
using 16 identical full adders (FA) as shown in the gure. The
carry-propagation delay of each FA is 12 ns and the sum
propagation delay of each FA is 15 ns. The worst case delay (in ns)
of this 16-bit adder will be
Answer: For the 1
st
FA, the carry propagation delay is 12 ns. So
the 2
n
dFA will generate its carry after 24ns. Therefore, the worst
case delay is = (15*12) + 15 = 195 ns

36. Problem 3
[GATE ECE 2014 Set 4] A 16-bit ripple carry adder is realized
using 16 identical full adders (FA) as shown in the gure. The
carry-propagation delay of each FA is 12 ns and the sum
propagation delay of each FA is 15 ns. The worst case delay (in ns)
of this 16-bit adder will be
Answer: For the 1
st
FA, the carry propagation delay is 12 ns. So
the 2
n
dFA will generate its carry after 24ns. Therefore, the worst
case delay is = (15*12) + 15 = 195 ns

37. Thank You