Binary multipliers

PPTs on Binary Multiplier

1. SYED HASAN SAEED

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2. BINARY MULTIPLIERS
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3. BINARY MULTIPLIERS

A Combinational multiplier is the logic circuit which is
implemented to perform multiplication.

The multiplicand is multiplied by each bit of the multiplier starting
from the least significant bit.

Each multiplication forms a partial product, successive partial
products are shifted one position to the left.

The final product is obtained from the sum of the partial products.
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2-bit by 2-bit Binary Multiplier:



2-Bit By 2-Bit
Multiplier
A
B
A
1A
O
B
1B
O
P=P
3P
2P
1P
O
FIG. 1

5. (i) 2-bit by 2-bit Binary Multiplier:
Consider the following multiplication of two 2-bit number
B
1 B
O
A
1 A
O Multiplier

A
OB
1 A
OB
O
A
1B
1 A
1B
O
P
3 P
2 P
1 P
O

P
O = A
OB
O
P
1=A
OB
1+A
1B
O
P
2=A
1B
1+ C
1
P
3= C
2

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Multiplicand
Partial Product 1
Partial Product 2
C
1
C
1
C
2
C
2
X
Final Result

6. IMPLEMENTATION OF GATES
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A
O
B
O
P
O
B
O
A
1
A
O
B
1
A
1
B
1
P
1
P
2
P
3 C
2=
C
1
A
1B
O
A
OB
1
A
1B
1
HA
HA
P
O = A
OB
O
P
1=A
OB
1+A
1B
O
P
2=A
1B
1+ C
1
P
3= C
2


FIG. 2

7. Multiplicand Bits are B
1 and B
O, Multiplier bits are A
1 and A
O and
the products is P
3P
2P
1P
O.
First partial product is formed by multiplying B
O by A
O and B
1 by
A
O
Multiplication of A
O and B
O produces 1, if both bits are 1;
otherwise it produces 0. This indicates an AND operation.
Therefore partial product can be implemented with AND gates.
The second partial product can be obtained by multiplying B
O by A
1
and B
1 by A
1 and shifted one position to the left.
The two partial product are added with two half adder circuits.
Usually there are more bits in the partial products and it is
necessary to use full adder to produce the sum of partial products.
2-bit by 2-bit Binary Multiplier shown in fig.3



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HA HA
B
O B
1
B
O B
1
A
O
A
1
Fig. 3: 2
-
Bit by 2
-
Bit Binary Multiplier

P
O P
1
P
2
P
3

9. B
3B
2B
1B
O
A
2A
1A
O

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A
OB
3 A
OB
2 A
OB
1 A
OB
O
A
1B
3 A
1B
2 A
1B
1 A
1B
O


(ii) 4-Bit By 3-Bit Binary Multiplier
C
O
C
1
C
2
S
O
S
1 S
2 S
3
A
2B
3 A
2B
2 A
2B
1 A
2B
O
C
3
C
4 C
5
S
4
S
5
S
6 C
6
P
O
P
1
P
2 P
3
P
4 P
5
P
6
Multiplicand
Multiplier
Partial Product 1
Partial Product 2
Partial Sum 1
Partial Product 3
Partial Sum 2
Final Result

10. •The partial product terms are produced via bit by bit multiplication.
This is equivalent to ANDing of two bits.
•Finally the partial product terms in each column are added together
to get final product terms.
• No. of AND gates= m * n, where m= multiplier bits and
n= multiplicand bits.
•(m-1)n-bit adders required to produce a product of m+n bits.
•For 4-bit by 3-bit multiplier, the no. of AND gates=3*4=12
•Two 4-bit adders are required to produce product of seven bits.
•Fig. 2 shows the 4-bit by 3-bit multiplier.
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11. (ii) 4-Bit By 3-Bit Binary Multiplier:

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B
2 B
1
B
O B
3
B
O B
1 B
2 B
3
ADDEND AUGEND
SUM AND OUTPUT CARRY
ADDEND AUGEND
SUM AND OUTPUT CARRY
4-BIT ADDER
4-BIT ADDER
A
O
A
1
A
2
P
O P
1
P
2
P
3
P
4
P
5
P
6
0
B
O
B
1
B
2 B
3
A
O
B
O

A
O
B
1

A
O
B
2

A
O
B
3
A
1
B
O

A
1
B
1

A
1
B
2

A
1
B
3

A
O
B
1

+
A
1
B
O

S
O
FIG. 4

12. (iii) 4- Bit By 4-Bit Binary Multiplier:
It is a combinational circuit. This logic circuit is implemented to
perform multiplication of two 4-bit binary numbers A= A
3A
2A
1A
O
and B=B
3B
2B
1B
O
A
3 A
2 A
1 A
O
B
3 B
2 B
1 B
O

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B
OA
3 B
OA
2 B
OA
1 B
OA
O
B
1A
3 B
1A
2 B
1A
1 B
1A
O
B
2A
3 B
2A
2 B
2A
1 B
2A
O
B
3A
3 B
3A
2 B
3A
1 B
3A
O
C
O
C
1 C
2
S
O
S
1 S
2 S
3 C
3
C
4 C
5 C
6
S
4
S
5 S
6
S
7 C
7
C
8
C
9 C
10
S
8
S
9 S
10
S
11 C
11
P
O P
1
P
2 P
3 P
4 P
5
P
6
P
7
Multiplicand
Multiplier
Partial Product 1
Partial Product 2
Partial Product 3
Partial Sum 1
Partial Product 4
Partial Sum 2
Partial Sum 3
Final Result

13. In this process the first partial product is obtained by multiplying B
O
with A
3A
2A
1A
O , the second partial product is formed by
multiplying B
1 with A
3A
2A
1A
O , likewise for III and IV partial
products.
These partial products can be implemented with AND gates (as
shown in fig.)
These partial product are then added by using 4 bit parallel adder.
The three most significant bits of first partial product with carry
(considered as zero) are added with second partial term in first full
adder.
Then the result is added to the next partial product with carry out
and it goes on till the final partial product, finally it produces 8 bit
sum which indicates the multiplication of two binary numbers.

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A
1
A
O
A
2 A
3
A
3 A
2
A
1 A
O
A
3
A
2 A
1
A
O
A
3
A
O A
1 A
2
B
O
B
1
B
3
B
2
P
O P
1 P
6
A
O
B
O

B
O
A
1
+B
1
A
O

P
3
P
5 P
2
P
7 P
4
4- Bit Binary Adder 1
4- Bit Binary Adder 2
4- Bit Binary Adder 3
S
O S
1 S
2 S
3
C
out

S
4 S
5 S
6 S
7
C
out

S
8 S
9 S
10
S
11
FIG. 4
: 4
-
Bit By 4
-
Bit Binary Parallel
Multiplier

0

15. References:
•Digital Design, Pearson, 4
th
Edition.
•Digital Circuit and Design, S. Salivahanan and S. Arivazhagan,
Oxford University Press, 5
th
Edition.
•Digital Systems Principles & Applications, Ronald J. Tocci,
Prentice-Hall of India Pvt. Ltd. , 6
th
Edition.
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16. THANK YOU
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