Bistables-multivibrators .pptx

process

1. We have dealt with combinational circuits (digital ccts without memory). Multivibrators circuits are mostly made up of both combinational circuits and memory elements. They include : - Mono-stables - Bistables - Astables Multivibrators

2. Bistables . Bistables: Devices which have two stable states(SET and RESET) They can retain either of these states indefinitely, making them useful as storage devices. Two categories of bistables : - the latch - the flip-flop Latches and Flip-flops differ, basically, in the way in which they are changed from one state from the other. Digital systems 1

3. Latch Latch ; A temporary memory devices which has two stable states. The latch can be an active-HIGH input S-R(SET-RESET) or an active-LOW input S-R(SET-RESET) as shown blow Digital systems 1

4. Active low Latch Digital systems 1 SET (output is high) condition RESET (output is low) condition

5. Active low Latch Digital systems 1 NO CHANGE and INVALID CONDITION

6. Active low Latch Digital systems 1 The logic symbols of both active low and active high latch The truth table of active low latch

7. Active low Latch Digital systems 1 The logic symbols of both active low and active high latch The truth table of active low latch

8. Active low Latch Digital systems 1 Example : The waveforms shown below are applied to the inputs of the active low latch. Assume initially that Q = 0, and determine the Q waveform

9. Active low Latch Digital systems 1 Example : The waveforms shown below are applied to the inputs of the active low latch. Assume initially that Q = 0, and determine the Q waveform

10. The gated Latch Digital systems 1 It has enable input ( EN or G) The inputs ,S and R, affects output only when EN is high Notice logic diagram and logic symbol for latch below Example : determine the Q output waveform

11. The D type bistable Digital systems 1 It has only one control input D(data) and enable input ( EN or G) The control input, D, affects output only when EN is high Notice logic diagram and logic symbol for D latch below Example : determine the Q output waveform

12. J-K Edge triggered Flip-Flops Digital systems 1 Flip flops are generally synchronous bistables Thus output changes state at specified point of triggering(CLK) input The state either changes at the +ve edge or –ve edge. J-K flip-flop is similar to S-R flip flop but it does not have invalid state. J-K flip flop have a toggle state as opposed to invalid state of S-R Notice the logic diagram and the truth table of J-K flip flop

13. J-K Edge triggered Flip-Flops Flip flops are generally synchronous bistables Thus output changes state at specified point of triggering(CLK) input The state either changes at the +ve edge or –ve edge. J-K flip-flop is similar to S-R flip flop but is does not have invalid state. J-K flip flop have a toggle state as opposed to invalid state of S-R Notice the logic diagram, symbol and the truth table of J-K flip flop +ve edge Example : determine the Q output waveform

14. J-K Edge triggered Flip-Flops Flip flops are generally synchronous bistables Thus output changes state at specified point of triggering(CLK) input The state either changes at the +ve edge or –ve edge. J-K flip-flop is similar to S-R flip flop but is does not have invalid state. J-K flip flop have a toggle state as opposed to invalid state of S-R Notice the logic diagram, symbol and the truth table of J-K flip flop +ve edge Example : determine the Q output waveform

15. J-K Edge triggered Flip-Flops Flip flops are generally synchronous bistables Thus output changes state at specified point of triggering(CLK) input The state either changes at the +ve edge or –ve edge. J-K flip-flop is similar to S-R flip flop but is does not have invalid state. J-K flip flop have a toggle state as opposed to invalid state of S-R Notice the logic diagram, symbol and the truth table of J-K flip flop Example : determine the Q output waveform -ve edge

16. Asynchronous Preset and Clear Inputs Flip flops are generally synchronous bistables Thus output changes state at specified point of triggering(CLK) input The state either changes at the +ve edge or –ve edge. J-K flip-flop is similar to S-R flip flop but is does not have invalid state. J-K flip flop have a toggle state as opposed to invalid state of S-R Notice the logic diagram, symbol and the truth table of J-K flip flop Example : determine the Q output waveform -ve edge

17. 555 Timer Versatile and Widely used IC Can be configured in monostable mode and Astable mode Structure

18. monostable mode Versatile and Widely used IC Can be configured in monostable mode and Astable mode Operation

19. monostable mode Versatile and Widely used IC Can be configured in monostable mode and Astable mode Operation