Cache Memory 01 _ Class Notes about computer organization and architecture foor gatecse

computer organization

1. Computer organization
and Architecture

2. Cache Memory

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2 =16 (Giga)
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Imeece 16 RO
U Sec = Io Sec.
MSEC = 10 TSC -

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8. Memory Hierarchy

Q Hierarchy design organize the system supported memory into
4 levels to minimize the Accessing times. They are:

9. Performance ——

Execuhon Time.

11. Total Nuwben of, Acceze

© Y Garhi Rabo 50].

Lie od po, B0Time Here ig Hip in Cache
C Reference gama h Cache].

14. MM 4o Cache :
O Dixect Mob

Set Assoc tahye Mobb er
5 Full, Associate ete ep =

15. à ol fu ne Mois

16. Memory
+ CPU generate Request will Regen to He Come

Hoy is Coled Corre Hit Coberotion is Called Hit)

Ha Respective Dafa ghe som Cod do CP) inthe form
o) Ino.

"TE He Referomce 12 Not found in the Coupe, frat ig tnown ax
Gus Miss, Hon Reference forwarded to Main Men

17. @
Memory
“Th te Reforemce found in the Main Meme kon Hs Giles}
MM Hit @ foe Hit. on Rerbective Dale gen from
Mon Mewiors do Cache in the form of Local Cache do CPU
bd Leu Y Word.
Th He Relaone ia Not Qoved in the Moin Meme that it @llesl

Mm Miss @ Page fout thon Repleme fines 4o sonde Memon .
© Stada pto she Lo Lo mary Gi Leo chs 1

18. Memory ®
& Rahectve Data it Franfaed from Secondary Pon
+ Mon Mene in He frm of, Pares, Main Memes do
Gave Mowe in he tym of Blocks, than oe. Memon
do CPU im AL Go of tajada.

* The Process of yanget the Data yom Main MONO do
Gike a it Ole. dr

19. Managed by H/W by H/W Physical address EN Virtual/Jogical

Managed by OS

20. Avesrage_ Mowers Accra tme Cova |

Tow =

eee Ee cer

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ls daken m by
bre bars amiss

21. © Gian CPU gemansie 100 Reqvar . Ot of 100 > ohms Hit

& lo was Mics. When Hue ie H
ig Qovsec , & wm fue is a Miss Juem tie Joan 12 150086

CGotudode Hre Toy?
E) Totes. CPU Requext = loo
Hit = ao Tes
Miss — lo Times
Li ii dales = 2VReC
Miss Ltd Jokes - Sec
Total Tree = 90x20 +10 1150
p = 1800 + 1500

FON Tnt = 3 3yonze

À Hum Hime token

joe ob
Total CPU Reyest=|00 Se
Hit = dou Miss = 10 Tw ©

bit AO) i 1-09 (1-
Ron: 2 —0.4 me ae (i-4)

Tag = HA Tree temita + (1H) [lineaire
: ad Hee is o iE m ) tete

a Mi
3 0:4X 20 + O-L (159) ”

3 18415
b

22. & Graian CPU gousse Yoo Penvet . OF 4 ZOO times Hit
loo times Mics. tren the 12 Hit them Hime taken

ig Qovsec , & wham fuue Isa Mics diem Five delta 12 150w8ec

Core the E os
Pas | Total CPU Reyest= 400 el
& Le Request =4oo À ht = wm Mies = 100 @
= 30 ;
Miss — : Hit Rohp = Y i -H)= (1-07
Ht ne aweec 1 y e 05 pes 2U Be s)
Miss With dokes + Idec :
Total Tres Zoo Y 20 + 100*1 50 : = MK Twe Tokenuhon +) Twetakem
=Go00+ 15000: *e Hee is o HE ) Se

m | ue
: 3 1512375 :

hy YD = 52 Grec
BO Cat

23. E

CPU & Gun ES MM SM
ya -Coara. [ Leahucion (ave)
Cao | D- Odre_ [Doda Care)

Lz Gure

24. Type of Memory Org

A Simultaneous Access Memory Org.

AZ Hierarchical Access Memory Org.

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25. @

Type of Memory Org

Simubloner P|
1. Simultaneous Access Memory Org. : (Ro Mowery Accæ Sí q ||

h: Ht Ratio

y = ht +LI=h) ty

26. @

Type of Memory Org

1. Simultaneous Access Memory Org.

Tr He Gmultetous Auen oR ALL He
Love of, Mere is Disedy Connected
Fo CPU. Rub faltas in Sequence (AL Me
Wham Hure is A Miss in Level L Many Huw
Reference trons to Leu 2_ (ewer. li
Me Ie Ht in Leyla Memo Hem
Diet Data is Ham pued from Lenol2. do

CPU tato! hp info LewL Memo

27. @

Type of Memory Org

1. Simultaneous Access Memory Org.
When He is o Miss in Lewll 2 level

SM DON 4 Hem led ? Memory Ha
(2) Ho, Ta Diectay Deda ia transfered from Leva

Memory to CPU Hop into
Hom Lordi 4 Lowel 2 Momo

28. @
Type of Memory Org hy: Hit Paño 4 loti OY

U): we Pati yi.
Simultaneous Access Memory Org.

Hae H, Ho Hn... He We nit Riom E

OHT Wk... a ae ec 4 fi

Tre Tiwe do Required do Acces (Pema |wok) toned
OL hom Mowsy

OL

E:

Tego lit ht (Ih) Ua) hata $
AED) ay

(i) Hn, Tre a AS

29. @
Type of Memory Org WwW

2. Hierarchical Access Memory Org.

- On He Hienardnical Access CPU ie Communicohgn With Ody (on Memos

ae is à Miss in level 2. Hittin Level 2 Mem hun’
Bt Dada ic taangexed from Lesl2 Memtay 4o LL Mean Ku
Lak Mead do CPU. 7 E Y

30. E

Type of Memory Org

2. Hierarchical Access Memory Org.

ML HT Het Ha Ty

OO)
Whom Hue IS à Miss in LedlL preto Many 2 Li in level Mow
hum fist Dore ic transfered fom Level 2( U2) Mung) do net] md,
Han Lerlo[L,) Mamay ty a Hm drow
TER) Memo to CPU.

31. @
Type of Memory Org WwW

2. Hierarchical Access Memory Org.

Tage BTL + (1-H) Ha (+75) + (MU) H
HEMI (1 y D He (Tat Toth) +

ie «lo Mm.) Hal Tat Tract: ++)
Dar Leu Hil Ro =L.

32. @ Dh in a Quehon Metiovedt the kequed " jerarcical

Access’ @ lend of Arcess ED Hieraus Seal
Hom Us; Higurducan ACCeB.

33. Calculate the average Access time with the cache access time 1ns, @
and main memory access time 100ns, Hit ratio 90%?
Using Hierarchical Access?

& te = nsec h = 90%:
Am = |00 Kec h-o49

Tog = het + (IN) Em ++)

3091 + (1-04) (Iov +1)
= 094 (0) (lol)
=04 +.)

34. In a 2 level memory, level 1 memory is 5 times faster than level 2. @
and its access time is 10ns < Average Access Time. Let level 1

Access time is 20ns, What is the hit ratio? Using simultaneous
Access feet] L3T
6) B= Pu ES LS T By = he +Uh) tm

PL 2 Qo = Hx 20 + (1-4) loo
5 = TR Ti = Ty —10 Ro = 20H 4100 —\oo}
0 9 30H = 70
act os
Pa 520 ‘Te 2018 387.5). yy

(ww) Tag: Tr+lo 3 20 Ho

35. Consider a system with 2 levels. Level 1 Access time is 20ns Level @
Access time = 150ns T,,, = 30 using simultaneous Access.
(i) Whatis the Hit Ratio?

ED If the Hit Ratio is mode to 100% then what is the Access
time of L, & L, Memory?

36. PN
If the above Question if T,, is increased by 10% then what is % ®

> of change in Hit Ratio?

37. Assume that for a certain processor, a read request takes 50
nanoseconds on a cache miss and 5 nanoseconds on a cache hit.
Suppose while running a program, it was observed that 80% of

the processor's read requests result i ache hit. The average
read access time in nanoseconds ¡ase fog [GATE - 2015]

Hit Ratio = 80 = 0-8

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