CAMP-V: Ultimate RISC-V Bootcamp sponsored by MERL and RISC-V

Slides for the CAMP-V, the Ultimate RISC-V Bootcamp.

1. CAMP-V
ULTIMATE RISC-V BOOTCAMP
and
presents

2. Welcome
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3. RISC-V Advocate
Research Associate @ MERL
CPU Design Engineer @ Intensivate
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4. AGENDA
Introductory Note10:00 AM
MERL Projects Showcase12:30 PM
Speed Programming2:00 PM
RISC-V Assembly Seminar10:30 AM
Lunch Break1:00 PM
Closing Note4:00 PM
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5. Research assistant @ MERL
lfx mentee 2023
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6. Instruction Set Architecture
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7. Instruction Set Architecture (ISA)
Defines how software controls hardware.
Two types of ISAs.
Complex Instruction Set Computer (CISC)
Reduced Instruction Set Computer (RISC)
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9. https://www.linkedin.com/posts/sidhant-jha-330223277_instruction-set-architecture-complete-flow-activity-7117942562757255168-v320/
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10. Complex Instruction Set Computer (CISC)
Supports complex instructions taking multiple clock cycles.
Supports variable-length instructions.
Consists of a few registers.
Example: x86
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11. Reduced Instruction Set Computer (RISC)
Supports simple instructions taking a single clock cycle.
Supports only fixed-length instructions.
Register count is big.
Example: ARM and RISC-V
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12. CISC vs RISC
CISC
Reduced code size.
Complex design.
Slower execution.
Greater power
consumption.
RISC
Greater code size.
Simpler design.
Faster execution.
Lower power
consumption.
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13. Quizizz
Password: merl1234
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14. RISC-V
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15. Background
Pronounced “risk-five”.
Developed in 2010 at University of California, Berkeley.
Fifth iteration of the RISC architecture.
Two variants: RV32 and RV64.
Extension based ISA.
RV32I as base extension.
M extension for multiplication instructions.
A extension for atomic instructions.
F extension for single-precision floating-point instructions.
D extension for double-precision floating-point instructions.
These extensions are collectively known as RV32G.
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16. RV32I Characteristics
32-bit general purpose integer registers named x0 through x31.
ABI names are standardized names for registers.
A RISC-V hart has byte-addressable address space.
32-bit register called a Program Counter (PC).
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17. Register Conventions
ABI name: zero
Value of the register is always
zero.
x0
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18. Register Conventions
ABI name: ra
Stores the return address of a
function call.
x1
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19. Register Conventions
ABI name: sp
Stores the address pointing to the
top of the stack in memory.
x2
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20. Register Conventions
ABI name: gp
Stores the address pointing to the
segment of memory holding global
variables (aka the data section).
gp
x3
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21. Register Conventions
ABI name: tp
Stores the address pointing to the
thread-local storage area of
memory containing data unique to
each thread.
x4
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22. Register Conventions
ABI names: t0-t2, t3-t6
Stores temporary data or data not
to be preserved between function
calls.
x5-x7
x28-x31
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23. Register Conventions
ABI names: s0/fp
Stores the address pointing to the
bottom of the current stack frame.
x8
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24. Register Conventions
ABI names: s1, s2-s11
Stores data that is to be preserved
between function calls.
x9
x18-x27
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25. Register Conventions
ABI name: a0-a7
These store function argument
values.
a0-a1 registers also store the return
values of functions.
x10-x17
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26. Quizizz
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27. RISC-V Assembly
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28. Assembly
Low-level programming language.
Strong correspondence between assembly instructions and machine language.
Direct communication with hardware.
All compilers and interpreters compile or interpret to assembly.
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29. RISC-V Assembly
Types of instructions
Computational
register-register
register-immediate
Conditional Jumps
Unconditional Jumps
Memory operations
Supplementary
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30. Computational Instructions
Register-register instructions
Format: inst rd, rs1, rs2
Register-immediate instructions
Format: inst rd, rs1, imm
Arithmetic Comparison Logical Shifts
Register-register add, sub slt, sltu and, or, xor sll, srl, sra
Register-immediate addi slti, sltiu andi, ori, xori slli, srli, srai
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31. Register-register instruction encoding
Computational Instructions
Register-immediate instruction encoding
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32. Instruction beq bne blt bltu bge bgeu
Operation == != < < >= >=
Conditional Jumps or Branch Instructions
If the condition is true, jump to the label.
Format: inst rs1, rs2, label
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33. Conditional Jumps or Branch Instructions
Used in if and loop conditions.
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34. Branch instruction encoding
Conditional Jumps or Branch Instructions
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35. Unconditional Jumps
If this instruction is encountered, jump to the label or address.
The address of the instruction following the jump instruction is saved to the
destination register.
jal: Jump and Link
Jump target specified as label.
Format: jal rd, label
jalr: Jump and Link Register
Jump target specified as sum of register value and constant offset.
Format: jalr, rd, rs1, imm
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36. Unconditional Jumps
Used in function calls.
jal is used to jump to function definition.
jalr is used to return from the function call.
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37. Unconditional Jumps
jal instruction encoding
jalr instruction encoding
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38. Instructions for communicating with memory.
Load instruction.
Reads data from memory.
Format: lw rd, imm(rs1)
Store instruction.
Writes data to memory.
Format: sw rs2, imm(rs1)
Memory Operation Instructions
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39. Memory Operation Instructions
Load instruction encoding
Store instruction encoding
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40. Supplementary Instructions
To be used in conjunction with other instructions.
lui: Load Upper-Immediate
loads the 20-bit immediate into the upper 20 bits of rd.
Used to build 32-bit constants.
auipc: Add Upper-Immediate to PC
loads the 20-bit immediate into the upper 20-bits, adding this offset to the PC.
Used to build PC-relative addresses.
Format: inst rd, imm
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41. Supplementary Instructions
Supplementary instruction encoding
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42. Quizizz
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