ch 2_Component and function of computer .pptx

this is ppt describe about computer components

1. Chapter 2 Computer Function and Interconnection 1

2. Von Newmann architecture It is based on three key concepts: Data and instructions are stored in a single read-write memory. The contents of this memory are addressable by location, without regard to the type of data contained there. Execution occurs in a sequential fashion from one instruction to the next. All contemporary computer designs are based on concepts developed by John von Neum ann 2

3. Hardwired program : A set of basic logic components can be combined in a way to perform arithmetic and logical operations on the data (e.g. a configuration of logic components can be designed to do specific calculation). The process of connecting these components produce a program in the form of hardware Results Data Sequece of arithmetic and logic functions Programming in hardwired 3

4. Software Program Software: Instead of rewiring the hardware for each new program, all we need to do is provide a new sequence of codes. Each code is, in effect, an instruction, and part of the hardware interprets each instruction and generates control signals. Results Instruction codes Instruction Interpreter Programming in software General-purpose aritmetic and logic functions Data Control signals 4

5. Programming in software: CPU Components So, we can say, the CPU consists of an instruction interpreter a module for general purpose arithmetic and logic functions Other components are needed 5

6. Programming in software: Other Components I/O component for accepting data and instruction in some form and converting them into an internal form of signals usable by the system, and for reporting results in the form of an output module. Memory module (main memory) is a place where to store temporarily both data and instructions 6

7. Computer Component: Top Level View CPU exchanges data with memory using MBR for data & MAR for addresses. I/O AR specifies a particular I/O device, and the I/O BR is used to exchange data between an I/O module and the CPU A Memory module consists of locations addressable by numbers. I/O module transfers data from external devices to CPU and memory, and vice versa. 7

8. Registers In a  computer , the  Memory Address Register (MAR)  is a  CPU  register that either stores the  memory address  from which data will be fetched to the CPU or the address to which data will be sent and stored. An  instruction register (IR)  is the part of a  CPU 's  control unit  that stores the address of the next instruction currently being executed or decoded. A  Memory Buffer Register  (MBR) is the register in a  computer 's processor, or  central processing unit , CPU, that stores the data being transferred to and from the immediate access store. It contains the copy of designated memory locations specified by MAR. It acts as a  buffer  allowing the processor and  memory units  to act independently without being affected by minor differences in operation. A data item will be copied to the MBR ready for use at the next  clock  cycle, when it can be either used by the processor for reading or writing or stored in main memory after being written.

9. Computer Basic Function The basic function performed by a computer is execution of a program , which consists of a set of instructions stored in memory. The instruction is in the form of a binary code that specifies what action the CPU is to take. Instruction processing consists of two steps: 9

10. Fetch/Execute Cycle Instruction fetching : gets an instruction from memory Instruction execution : performs the instruction 10

11. Fetch cycle Fetch cycle Program Counter (PC) holds address of next instruction to fetch Processor fetches instruction from memory location pointed to by PC Increment PC (Unless told otherwise (branch)) The fetched Instruction loaded into Instruction Register (IR) 11

12. Fetching an Instruction 0001 Instruction Pointer 0001 0002 0003 0004 0005 Memory location contents 0FFF 0FA0 010D 00C1 0010 Address Bus 12

13. Fetching an Instruction 0001 Instruction Pointer 0001 0002 0003 0004 0005 Memory location contents 0FFF 0FA0 010D 00C1 0010 Address Bus Contents of the Program Counter are passed across the Address Bus 13

14. Fetching an Instruction 0001 Instruction Pointer 0001 0002 0003 0004 0005 Memory location contents 0FFF 0FA0 010D 00C1 0010 Address Bus 0001 Memory Access Register The address moves over the address bus to the Memory Access Register 14

15. Fetching an Instruction 0001 0002 0003 0004 0005 Memory location contents 0FFF 0FA0 010D 00C1 0010 0001 Memory Access Register The memory location of the next instruction is located. 15

16. Fetching an Instruction 0001 0002 0003 0004 0005 Memory location contents 0FFF 0FA0 010D 00C1 0010 Data Bus The contents of memory at the given location are moved across the data bus 16

17. Fetching an Instruction 0001 0002 0003 0004 0005 Memory location contents 0FFF 0FA0 010D 00C1 0010 0FFF Instruction Register Data Bus Into the instruction register (IR) 17

18. Fetching an Instruction 0FFF Instruction Register With the instruction loaded from memory into the Instruction Register the fetch portion of the cycle is complete. 18

19. Execute Cycle Processor interprets instruction and performs required actions: Data transfer Between CPU and main memory Between CPU and I/O module Data processing Some arithmetic or logical operation on data Control Alteration of sequence of operations, e.g. jump Combinations of the above

20. Processor Fetch, Decode and Execute Cycle.

21. Characteristics of a Hypothetical Machine

22. Example of Program Execution

23. From the example above example. . . 23

24. Instruction Cycle state diagram iac : determines the address of the next instruction to be executed if : fetch (read) instruction from memory location into the processor 24

25. Instruction Cycle state diagram iod : decode (analyze) instruction to determine type of operation to be performed and operand/s to be used oac : (operand address calculation) determine the address of the operand (in memory or I/O) if the instruction has a reference to an operand. of : fetch the operand from memory or read it in from I/O do : (data Operation) perform the operation indicated in the instruction os (operand store): Write the result into memory or out to I/O 25

26. Notice that: The upper part of the diagram involve data exchanging between the CPU and either the memory or an I/O module, while the lower part involve only internal processor operations 26

27. Interrupts Interrupt is a mechanism by which other modules (e.g. I/O, memory) may interrupt the normal processing of the processor. Its main goal is to improve processing efficiency since the external devices (e.g. I/O modules) are very slow. CPU may waste time waiting for these slow devices to perform their tasks With interrupts, the processor can be engaged in executing other instructions while an I/O operation is in progress. 27

28. Interrupts Example : Without interrupts, the processor will set idle after each write operation until the printer is catching up. The length of the pause may be in order of thousands of instructions cycles that don’t involve memory. It is wasteful! 28

29. Interrupts Classes of interrupts   Program: Generated by some condition that occurs as a result of an instruction execution, such as arithmetic overflow, divide by zero, illegal memory use. Timer: Generated by a timer within the processor. It allows the OS to perform certain functions on a regular basis. 29

30. Interrupts Classes of interrupts I/O: Generated by an I/O controller, to signal normal completion of an operation or to signal a variety of error conditions. 4. Hardware failure: Generated by a failure such as power failure or memory parity error. 30

31. Interrupts 31

32. Interrupt Cycle Added to instruction cycle Processor checks for interrupt Indicated by an interrupt signal If no interrupt, fetch next instruction If interrupt pending: Suspend execution of current program Save context Set PC to start address of interrupt handler routine Process interrupt Restore context and continue interrupted program

33. Transfer of Control via Interrupts

34. Interrupts: Instruction cycle with interrupts 34

35. The revised instruction cycle state diagram that includes interrupt cycle processing 35

36. Multiple interrupts Example: A program may be receiving data from a communication line and printing results. So, the printer will generates an interrupt every time that it completes a print operation, and the communication line controller will generate an interrupt every time a unit of data arrives. 36

37. Multiple interrupts It is possible for a communication interrupt to occur while a printer interrupt is being processed. So what will happen: Two approaches: Disable interrupts Define priorities 37

38. Multiple interrupts Disable interrupts Processor will ignore further interrupts whilst processing one interrupt Interrupts remain pending and are checked after first interrupt has been processed Interrupts are handled in sequence as they occur 38

39. Interrupts: sequential interrupt processing 39

40. Multiple interrupts Define priorities Low priority interrupts can be interrupted by higher priority interrupts When higher priority interrupt has been processed, processor returns to previous interrupt 40

41. Interrupts: nested interrupts processing 41

42. Interconnection Structures All the units must be connected Interconnection structure: The collection of paths connecting system modules Different type of connection for different type of unit Memory Input/output CPU Design depends on necessary exchanges between modules 42

43. Data Transfer The interconnection structure must support the following types of transfers: Memory to processor: The processor reads an instruction or a unit of data from memory. Processor to memory: The processor writes a unit of data to memory. I/O to processor: The processor reads data from an I/O device via an I/O module. Processor to I/O: The processor sends data to the I/O device . I/O to or from memory: For these two cases, an I/O module is allowed to exchange data directly with memory, without going through the processor, using direct memory access (DMA). 43

44. Computer Modules 44

45. Bus Interconnection A bus is a communication pathway connecting two or more device. A key characteristic of a bus is that it is a shared transmission medium. A bus consists of multiple pathways or lines. Each line is capable of transmitting signal representing binary digit (1 or 0) 45

46. Bus Interconnection A sequence of bits can be transmit across a single line. Several lines can be used to transmit bits simultaneously (in parallel). A bus that connects major components (CPU,Memory,I/O) is called System Bus . The most common computer interconnection structures are based on the use of one or more system buses. 46

47. Bus Structure A system bus consists of 50-100 lines. Each line is assigned a particular meaning or function. On any bus the lines can be classified into 3 groups Data lines Address lines Control lines 47

48. Data Lines Provide a path for moving data between system modules. These lines, collectively, are called the data bus The data bus typically consists of 8,16 or 32 separate lines, the numbers of lines being transferred to as the width of the data bus. Each line carry only 1 bit at a time, the number of lines determines how many bits can transferred at a time - overall system performance. 48

49. The Address Lines Used to designate the source or destination of the data on the data bus e.g. CPU needs to read an instruction (data) from a given location in memory T he width of the address bus determines the maximum possible memory capacity of the system. e.g. 8080 has 16 bit address bus giving 64k address space 49

50. The Control Lines Used to control the access to and the use of the data and address lines . Memory read/write signal Interrupt request Clock signals Typical control lines include Memory write Memory read I/O write I/O read Clock Reset Bus request Bus grant Interrupt request Interrupt ACK Transfer ACK 50

51. Typical Control Lines: Memory write: causes data on the bus to be written into the addressed location. Memory read: causes data from the addressed location to be placed on the bus. I/O write: causes data on the bus to be output to the addressed I/O port. I/O read: causes data from the addressed I/O port to be placed on the bus. Transfer ACK: indicates that data have been accepted from or placed on the bus. Bus Request: indicates that a module needs to gain control of the bus. Bus Grant: indicates that the requesting module has been granted control of the bus. Interrupt Request: Indicates that an interrupt is pending. Interrupt ACK: Acknowledges that the pending interrupt has been recognized. Clock: Is used to synchronize operations Reset: Initializes all modules

52. Physical Realization of Bus Architecture

53. Single Bus Problems Lots of devices on one bus leads to: Propagation delays Long data paths mean that co-ordination of bus use can adversely affect performance If aggregate data transfer approaches bus capacity Most systems use multiple buses to overcome these problems

54. What do buses look like ? 54 Parallel lines on circuit boards Ribbon cables Strip connectors on mother boards e.g. PCI Sets of wires ?

55. Traditional (ISA) (with cache)

56. Traditional Bus Architecture Local bus CPU - Cache System bus Main memory - Cache Expansion bus I/O Modules - Main memory 56

57. High-Performance Architecture Local bus CPU - Cache/bridge System bus Cache/bridge - memory High-speed bus High-speed I/O module - Cache/bridge Expansion bus Low-speed I/O modules - Expansion interface 57

58. 58

59. If a great number of devices are connected to the bus, performance will suffer because: In general, the more devices attached to the bus, the greater the bus length and greater delay. Bus may become a bottleneck as the aggregate data transfer demand approaches the capacity of the bus. So.. Because of this, it is important to have a hierarchy. Multiple-Bus Hierarchies

60. Elements of Bus Design Method of Arbitration Centralized Distributed Data Transfer Type Read Write Read-modify-write Read-after-write Block 60

61. Bus Types Dedicated Separate data & address lines Multiplexed Shared lines Address valid or data valid control line Advantage - fewer lines Disadvantages More complex control Ultimate performance

62. Bus Width Address the wider of address bus has an impact on range of locations that can be referenced Data the wider of data bus has an impact on the number of bits transferred at one time Timing Refers to the way in which events are coordinated on the bus. Buses use either synchronous timing or asynchronous timing. Synchronous O ccurrence of events on the bus is determined by a clock (Clock Cycle or Bus Cycle) which includes line upon Asynchronous occurrence of one event follows and depends on the previous event. 62

63. Bus Arbitration More than one module may control the bus e.g. CPU and DMA controller Only one module may control bus at one time Arbitration may be centralised or distributed Centralised Single hardware device controlling bus access Bus Controller Arbiter May be part of CPU or separate Distributed Each module may claim the bus Control logic on all modules

64. Samples of Bus ISA (Industry Standard Architecture) EISA (Extended ISA) VL Bus (VESA Local Bus) PCI Bus (Peripheral Connection Interface) 64

65. Industry Standard Architecture ISA is a standard bus (computer interconnection) architecture that is associated with the IBM AT motherboard. It allows 16 bits at a time to flow between the motherboard circuitry and an expansion slot card and its associated device(s). 65

66. Extended Industry Standard Architecture EISA is a standard bus architecture that extends the ISA standard to a 32-bit interface. It was developed in part as an open alternative to the proprietary Micro Channel Architecture ( MCA ) that IBM introduced in its PS/2 computers. EISA data transfer can reach a peak of 33 megabytes per second 66

67. VESA Local Bus VESA VL bus is a standard interface between your computer and its expansion slot that provides faster data flow between the devices controlled by the expansion cards and your computer's microprocessor. A "local bus" is a physical path on which data flows at almost the speed of the microprocessor, increasing total system performance. 67

68. VESA Local Bus (cont.) VESA Local Bus is particularly effective in systems with advanced video cards and supports 32-bit data flow at 50 MHz A VESA Local Bus is implemented by adding a supplemental slot and card that aligns with and augments an ISA expansion card. (ISA is the most common expansion slot in today's computers.) 68

69. Peripheral Component Interconnect (PCI) PCI is an interconnection system between a microprocessor and attached devices in which expansion slot are spaced closely for high speed operation. Using PCI, a computer can support both new PCI cards while continuing to support ISA expansion cards, currently the most common kind of expansion card. 69

70. Peripheral Component Interconnect (cont.) Designed by Intel, the original PCI was similar to the VESA Local Bus. PCI2.0 is no longer a local bus and is designed to be independent of microprocessor design. PCI is designed to be synchronized with the clock speed of the microprocessor, in the range of 33 to 66 MHz. Standard : Up to 64 data-lines at 66 MHz. Raw transfer rate of 528 MBps or 4.224 Gbps. 70

71. Peripheral Component Interconnect (cont.) PCI is now installed on most new desktop computers, not only those based on Intel's Pentium processor but also those based on the PowerPC. PCI transmits 32 bits at a time in a 124-pin connection (the extra pins are for power supply and grounding) and 64 bits in a 188-pin connection in an expanded implementation. 71

72. Peripheral Component Interconnect (cont.) PCI uses all active paths to transmit both address and data signals, sending the address on one clock cycle and data on the next. PCI deliver better system performance for high-speed I/O subsystems e.g. graphic display adapters , network interface controllers , disk controllers 72