cmos-fabrication and nmos fabrication.ppt

vlsi design and fabrication

1. EE466: CMOS VLSI
Lecture 04: Fabrication

2. CMOS VLSI Design0: Introduction Slide 2
CMOS Fabrication
CMOS transistors are fabricated on silicon wafer
Lithography process similar to printing press
On each step, different materials are deposited or
etched
Easiest to understand by viewing both top and
cross-section of wafer in a simplified manufacturing
process

3. CMOS VLSI Design0: Introduction Slide 3
Inverter Cross-section
Typically use p-type substrate for nMOS transistors
Requires n-well for body of pMOS transistorsn+
p substrate
p+
n well
A
Y
GND V
DD
n+ p+
SiO
2
n+ diffusion
p+ diffusion
polysilicon
metal1
nMOS transistor pMOS transistor

4. CMOS VLSI Design0: Introduction Slide 4
Well and Substrate Taps
Substrate must be tied to GND and n-well to V
DD
Metal to lightly-doped semiconductor forms poor
connection called Shottky Diode
Use heavily doped well and substrate contacts / tapsn+
p substrate
p+
n well
A
Y
GND
V
DD
n+p+
substrate tap well tap
n+ p+

5. CMOS VLSI Design0: Introduction Slide 5
Inverter Mask Set
Transistors and wires are defined by masks
Cross-section taken along dashed lineGND V
DD
Y
A
substrate tap well tap
nMOS transistor pMOS transistor

6. CMOS VLSI Design0: Introduction Slide 6
Detailed Mask Views
Six masks
–n-well
–Polysilicon
–n+ diffusion
–p+ diffusion
–Contact
–MetalMetal
Polysilicon
Contact
n+ Diffusion
p+ Diffusion
n well

7. CMOS VLSI Design0: Introduction Slide 7
Fabrication Steps
Start with blank wafer
Build inverter from the bottom up
First step will be to form the n-well
–Cover wafer with protective layer of SiO
2(oxide)
–Remove layer where n-well should be built
–Implant or diffuse n dopants into exposed wafer
–Strip off SiO
2p substrate

8. CMOS VLSI Design0: Introduction Slide 8
Oxidation
Grow SiO
2on top of Si wafer
–900 –1200 C with H
2O or O
2in oxidation furnacep substrate
SiO
2

9. CMOS VLSI Design0: Introduction Slide 9
Photoresist
Spin on photoresist
–Photoresist is a light-sensitive organic polymer
–Softens where exposed to lightp substrate
SiO
2
Photoresist

10. CMOS VLSI Design0: Introduction Slide 10
Lithography
Expose photoresist through n-well mask
Strip off exposed photoresistp substrate
SiO
2
Photoresist

11. CMOS VLSI Design0: Introduction Slide 11
Etch
Etch oxide with hydrofluoric acid (HF)
–Seeps through skin and eats bone; nasty stuff!!!
Only attacks oxide where resist has been exposedp substrate
SiO
2
Photoresist

12. CMOS VLSI Design0: Introduction Slide 12
Strip Photoresist
Strip off remaining photoresist
–Use mixture of acids called piranah etch
Necessary so resist doesn’t melt in next stepp substrate
SiO
2

13. CMOS VLSI Design0: Introduction Slide 13
n-well
n-well is formed with diffusion or ion implantation
Diffusion
–Place wafer in furnace with arsenic gas
–Heat until As atoms diffuse into exposed Si
Ion Implanatation
–Blast wafer with beam of As ions
–Ions blocked by SiO
2, only enter exposed Sin well
SiO
2

14. CMOS VLSI Design0: Introduction Slide 14
Strip Oxide
Strip off the remaining oxide using HF
Back to bare wafer with n-well
Subsequent steps involve similar series of stepsp substrate
n well

15. CMOS VLSI Design0: Introduction Slide 15
Polysilicon
Deposit very thin layer of gate oxide
–< 20 Å(6-7 atomic layers)
Chemical Vapor Deposition (CVD) of silicon layer
–Place wafer in furnace with Silane gas (SiH
4)
–Forms many small crystals called polysilicon
–Heavily doped to be good conductorThin gate oxide
Polysilicon
p substrate
n well

16. CMOS VLSI Design0: Introduction Slide 16
Polysilicon Patterning
Use same lithography process to pattern polysiliconPolysilicon p substrate
Thin gate oxide
Polysilicon
n well

17. CMOS VLSI Design0: Introduction Slide 17
Self-Aligned Process
Use oxide and masking to expose where n+ dopants
should be diffused or implanted
N-diffusion forms nMOS source, drain, and n-well
contactp substrate
n well

18. CMOS VLSI Design0: Introduction Slide 18
N-diffusion
Pattern oxide and form n+ regions
Self-aligned processwhere gate blocks diffusion
Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processingp substrate
n well n+ Diffusion

19. CMOS VLSI Design0: Introduction Slide 19
N-diffusion cont.
Historically dopants were diffused
Usually ion implantation today
But regions are still called diffusionn well
p substrate
n+n+ n+

20. CMOS VLSI Design0: Introduction Slide 20
N-diffusion cont.
Strip off oxide to complete patterning stepn well
p substrate
n+n+ n+

21. CMOS VLSI Design0: Introduction Slide 21
P-Diffusion
Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contactp+ Diffusion p substrate
n well
n+n+ n+p+p+p+

22. CMOS VLSI Design0: Introduction Slide 22
Contacts
Now we need to wire together the devices
Cover chip with thick field oxide
Etch oxide where contact cuts are neededp substrate
Thick field oxide
n well
n+n+ n+p+p+p+ Contact

23. CMOS VLSI Design0: Introduction Slide 23
Metalization
Sputter on aluminum over whole wafer
Pattern to remove excess metal, leaving wiresp substrate
Metal
Thick field oxide
n well
n+n+ n+p+p+p+ Metal

24. CMOS VLSI Design0: Introduction Slide 24
Transistors as Switches
We can view MOS transistors as electrically
controlled switches
Voltage at gate controls path from source to draing
s
d
g = 0
s
d
g = 1
s
d
g
s
d
s
d
s
d
nMOS
pMOS
OFF
ON
ON
OFF

25. CMOS VLSI Design0: Introduction Slide 25
CMOS Inverter
AY
0
1V
DD
A Y
GND A Y

26. CMOS VLSI Design0: Introduction Slide 26
CMOS Inverter
AY
0
10V
DD
A=1 Y=0
GND
ON
OFF A Y

27. CMOS VLSI Design0: Introduction Slide 27
CMOS Inverter
AY
01
10V
DD
A=0 Y=1
GND
OFF
ON A Y

28. CMOS VLSI Design0: Introduction Slide 28
CMOS NAND Gate
ABY
00
01
10
11A
B
Y

29. CMOS VLSI Design0: Introduction Slide 29
CMOS NAND Gate
ABY
001
01
10
11A=0
B=0
Y=1
OFF
ON ON
OFF

30. CMOS VLSI Design0: Introduction Slide 30
CMOS NAND Gate
ABY
001
011
10
11A=0
B=1
Y=1
OFF
OFF ON
ON

31. CMOS VLSI Design0: Introduction Slide 31
CMOS NAND Gate
ABY
001
011
101
11A=1
B=0
Y=1
ON
ON OFF
OFF

32. CMOS VLSI Design0: Introduction Slide 32
CMOS NAND Gate
ABY
001
011
101
110A=1
B=1
Y=0
ON
OFF OFF
ON

33. CMOS VLSI Design0: Introduction Slide 33
CMOS NOR Gate
ABY
001
010
100
110 A
B
Y

34. CMOS VLSI Design0: Introduction Slide 34
3-input NAND Gate
Y pulls low if ALL inputs are 1
Y pulls high if ANY input is 0

35. CMOS VLSI Design0: Introduction Slide 35
3-input NAND Gate
Y pulls low if ALL inputs are 1
Y pulls high if ANY input is 0A
B
Y
C

36. CMOS VLSI Design0: Introduction Slide 36
Layout
Chips are specified with set of masks
Minimum dimensions of masks determine transistor
size (and hence speed, cost, and power)
Feature size f= distance between source and drain
–Set by minimum width of polysilicon
Feature size improves 30% every 3 years or so
Normalize for feature size when describing design
rules
Express rules in terms of l= f/2
–E.g. l= 0.3 mm in 0.6 mm process

37. CMOS VLSI Design0: Introduction Slide 37
Simplified Design Rules
Conservative rules to get you started

38. CMOS VLSI Design0: Introduction Slide 38
Inverter Layout
Transistor dimensions specified as Width / Length
–Minimum size is 4l/ 2l, sometimes called 1 unit
–In f= 0.6 mm process, this is 1.2 mm wide, 0.6 mm
long

39. CMOS VLSI Design0: Introduction Slide 39
Summary
MOS Transistors are stack of gate, oxide, silicon
Can be viewed as electrically controlled switches
Build logic gates out of switches
Draw masks to specify layout of transistors
Now you know everything necessary to start
designing schematics and layout for a simple chip!