CMOS_Processfor knowing thestepsinvolvedpdf

CMOS cmos

1. CMOS VLSI
Design
CMOS Processing
Peter Kogge
University of Notre Dame
Fall 2015, 2018
Based on material from
Prof. Jay Brockman, Joseph Nahas, University of Notre Dam
Prof. David Harris, Harvey Mudd College
http://www.cmosvlsi.com/coursematerials.html

2. CMOS VLSI DesignOutline
CMOS Physical Structure
Photolithography (Using light to define objects)
Positive
Negative
Fabrication Overview
Fabrication Step-by-Step
Etching (Removal of material)
Doping of Semiconductor (Adding donor and acceptors)
Deposition (Adding material on top of wafer)
Newer Processes CMOS Processing Slide 2

3. CMOS VLSI Design
CMOS Cross Sections
CMOS Processing Slide 3

4. CMOS VLSI Design
MOS Transistor Cross-section
Key Controlling Physical Parameters
Length(L) of channel
Width(W) of Channel
Thickness(t
ox
)of gate insulator
Material types
N-type: Phosphorous doped to provide “free” electrons
P-type: Boron doped to provide “free” positive holes
GATE
SOURCEDRAIN
CHANNEL
Length
Width
Thickness
Circuits-ASlide 4

5. CMOS VLSI Design CMOS Processing Slide 5
Inverter Cross-section
Typically use p-type substratefor nMOS transistors
Requires n-wellfor body of pMOS transistors
n+
p substrate
p+
n well
A
Y
GNDV
DD
n+p+
SiO
2
n+ diffusion
p+ diffusion
polysilicon
metal1
nMOS transistor pMOS transistor

6. CMOS VLSI Design
CMOS Technology Cross Section
CMOS Processing Slide 6
SiN

7. CMOS VLSI Design
TSMC 0.18 CMOS Cross Section
CMOS Processing Slide 7
Al Metal 1
Al Metal 2
Al Metal 3
W Contact
W Via 1
W Via 2
Drain
Shallow
Trench
Isolation
(STI)
Poly
Gate
Source
SiO
2

8. CMOS VLSI Design
130 nm transistor
CMOS Processing Slide 8
TiN
Poly Si Gate
Spacer
Source/Drain

9. CMOS VLSI Design
Photolithography
CMOS Processing Slide 9

10. CMOS VLSI Design
Photolithography
Aka "optical lithography“
Selectively remove parts of a
thin film on top of a substrate
or thebulkof a substrate.
Uses light to transfer geometric pattern
from photo mask
to light-sensitive chemical photo resist, (" resist”), on
the substrate.
Series of chemical treatments engraves
exposure pattern into material underneath the
photo resist. CMOS Processing Slide 10

11. CMOS VLSI Design
Exposure
CMOS Processing Slide 11
Quartz
Chrome Pattern
Lens
Substrate
Photosensitive PolymerImage
Light

12. CMOS VLSI Design
Photolithography Light
CMOS Processing Slide 12

13. CMOS VLSI Design
Photolithography
Process of transferring geometric shapes on a
mask(quartz glass plate) to the surface of a
silicon wafer.
Mask is created using a photolithographic
process with an electron beam to scan the
images on the plate. CMOS Processing Slide 13

14. CMOS VLSI Design
Photolithography
CMOS Processing Slide 14
Feature on mask
results in feature on silicon
Feature on mask
results in negative feature on silicon

15. CMOS VLSI Design
Fabrication Overview
CMOS Processing Slide 15

16. CMOS VLSI Design CMOS Processing Slide 16
CMOS Fabrication
CMOS transistors fabricated on silicon wafer
One wafer contains tens to thousands of chips
Today wafers are up to 300 mm across
Photolithographyprocess “prints” patterns on
the wafer.
On each step, different materials are deposited
or etched
Easiest to understand: view both top and cross-
sectionof wafer in a simplified manufacturing
process, circa 1980.

17. CMOS VLSI Design
CMOS Chips In Cross Section
IntroductionSlide 17
http://www.hitequest.com/Kiss/photolithography.gif
http://www.engr.sjsu.edu/WofMatE/images/intercon.gif

18. CMOS VLSI Design CMOS Processing Slide 18
Inverter Cross-section
Typically use p-type substratefor nMOS transistors
Requires n-wellfor body of pMOS transistors
n+
p substrate
p+
n well
A
Y
GNDV
DD
n+p+
SiO
2
n+ diffusion
p+ diffusion
polysilicon
metal1
nMOS transistor pMOS transistor

19. CMOS VLSI Design CMOS Processing Slide 19
Well and Substrate Taps
Process circa 1980
Modern processes much more complicated but more robust.
Substrate must be tied to GND and n-well to V
DD
Metal to lightly-doped semiconductor forms poor connection called
Schottky Diode
Very low threshold voltage
Use heavily doped well and substrate contacts / taps
n+
p substrate
p+
n well
A
Y
GND
V
DD
n+ p+
substrate tap
well tap
n+ p+

20. CMOS VLSI Design CMOS Processing Slide 20
Inverter 6 Mask Set
Transistors and wires are defined by sets of masks
2D pattern selectively allows/blocks access to chip surface
Each mask controls one kind of structure
Two views will be shown in the following slides
Mask view
Vertical cross-sectiontaken along dashed line (see previous slide)
GNDV
DD
Y
A
substrate tapwell tap
nMOS transistorpMOS transistor

21. CMOS VLSI Design CMOS Processing Slide 21
Mask Views
Six masks for a very simple process
n-well
Polysilicon
n+ diffusion
p+ diffusion
Contact
Metal
Metal
Polysilicon
Contact
n+ Diffusion
p+ Diffusion
n well

22. CMOS VLSI Design
Fabrication Step by Step
CMOS Processing Slide 22

23. CMOS VLSI Design
Silicon Growth
CMOS Processing Slide 23
Single
Crystal of
Silicon

24. CMOS VLSI Design CMOS Processing Slide 24
Fabrication Steps
Start with blank wafer
Build inverter from the bottom up
First step will be to form the n-well
Cover wafer with protective layer of SiO
2
(oxide)
Remove layer where n-well should be built
Implant or diffuse n dopants into exposed wafer
Strip off SiO
2
p substrate

25. CMOS VLSI Design CMOS Processing Slide 25
n-well: Oxidation
Grow SiO
2
on top of Si wafer
900 – 1200 C with H
2
O or O
2
in oxidation furnace
p substrate
SiO
2

26. CMOS VLSI Design CMOS Processing Slide 26
n-well: Photoresist
Spin on photoresist
Photoresist is a light-sensitive organic polymer
Softens (positive) or hardens (negative) where exposed to
light
p substrate
SiO
2
Photoresist

27. CMOS VLSI Design CMOS Processing Slide 27
n-well: Lithography
Expose photoresist through n-well mask
Strip off exposed photoresist
p substrate
SiO
2
Photoresist
Mask
Light

28. CMOS VLSI Design CMOS Processing Slide 28
n-well: Etch
Etch oxide with hydrofluoric acid (HF)
Seeps through skin and eats bone; nasty stuff!!!
Dry etch using plasma etch (CF
4
)
Only attacks oxide where resist has been exposed
p substrate
SiO
2
Photoresist

29. CMOS VLSI Design
Plasma Etching
CMOS Processing Slide 29

30. CMOS VLSI Design
Plasma Etcher
CMOS Processing Slide 30

31. CMOS VLSI Design CMOS Processing Slide 31
n-well: Diffusion
n-well is formed with diffusionor ion implantation
Diffusion
Place wafer in furnace with arsenic (As) gas
Heat until As atoms diffuse into exposed Si
Ion Implanatation
Blast wafer with beam of As ions
Ions blocked by SiO
2
, only enter exposed Si
n well
SiO
2

32. CMOS VLSI Design
Ion Implantation
CMOS Processing Slide 32

33. CMOS VLSI Design
Ion Implantation
Parameters
Acceleration Voltage
•Determines depth of implant
Integrated Current – Charge
•Determines amount of implant
CMOS Processing Slide 33

34. CMOS VLSI Design CMOS Processing Slide 34
n-well: Strip Oxide
Strip off the remaining oxide using HF
Back to bare wafer with n-well
Subsequent steps involve similar series of steps
p substrate
n well

35. CMOS VLSI Design
CMOS Processing
Slide 35
Forming the Gates
Deposit very thin layer of gate oxide
< 20 Å (6-7 atomic layers)
Chemical Vapor Deposition(CVD) of silicon layer
Place wafer in furnace with Silane gas (SiH
4
)
Forms many small crystals called polysilicon
Heavily doped to be good conductor
When the acronym “MOS” was invented, Al was used for
the gate, instead of polysilicon.
In 45 nm technology, metal gates and hafnium oxide are
used.
Thin gate oxide
Polysilicon
p substrate
n well

36. CMOS VLSI Design
Batch CVD
CMOS Processing Slide 36

37. CMOS VLSI Design
Plasma Assisted CVD
CMOS Processing Slide 37

38. CMOS VLSI Design
CVD Reactions
Silicon
SiH
4
→ Si + 2 H
2
Silicon Dioxide
SiH
4
+ O
2
→ SiO
2
+ 2 H
2
Silicon Nitride
3 SiH
4
+ 4 NH
3
→ Si
3
N
4
+ 12 H
2
Metal
2 MCl
5
+ 5 H
2
→ 2 M + 10 HCl
CMOS Processing Slide 38

39. CMOS VLSI Design CMOS Processing Slide 39
Gate: Polysilicon Patterning
Use same lithography process to pattern polysilicon
Polysilicon
p substrate
Thin gate oxide
Polysilicon
n well

40. CMOS VLSI Design CMOS Processing Slide 40
Transistor formation:
Self-Aligned Process
Use oxide and masking to expose where n+ dopants
should be diffused or implanted
N-diffusion forms nMOS source, drain, and n-well contact
p substrate
n well

41. CMOS VLSI Design CMOS Processing Slide 41
Transistor: N-diffusion
Pattern oxide and form n+ regions
Self-aligned processwhere gate blocks diffusion
Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing
p substrate
n well
n+ Diffusion

42. CMOS VLSI Design CMOS Processing Slide 42
Transistor: N-diffusion cont.
Historically dopants were diffused
Usually ion implantation today
But regions are still called diffusion
n well
p substrate
n+ n+
n+

43. CMOS VLSI Design CMOS Processing Slide 43
Transistor: N-diffusion cont.
Strip off oxide to complete patterning step
n well
p substrate
n+ n+
n+

44. CMOS VLSI Design CMOS Processing Slide 44
Transistor: P-Diffusion
Similar set of steps form p+ diffusion regions for pMOS
source and drain and substrate contact
p+ Diffusion
p substrate
n well
n+ n+
n+
p+ p+ p+

45. CMOS VLSI Design CMOS Processing Slide 45
Forming Contacts
Now we need to wire together the devices
Cover chip with thick field oxide
Etch oxide where contact cuts are needed
p substrate
Thick field oxide
n well
n+ n+
n+
p+ p+ p+
Contact

46. CMOS VLSI Design CMOS Processing Slide 46
Metalization
Sputter on aluminum over whole wafer
Pattern to remove excess metal, leaving wires
p substrate
Metal
Thick field oxide
n well
n+ n+
n+
p+ p+ p+
Metal

47. CMOS VLSI Design
Sputter Deposition
CMOS Processing Slide 47

48. CMOS VLSI Design
Advanced Processes
CMOS Processing Slide 48

49. CMOS VLSI Design
CMOS Processing Slide 49
Twin Tub CMOS w/STI & Al-W metal
n-poly
p-poly
metal (Al)
Drain
Source
Drain
Source
NMOS
PMOS
contact (W)
P- Epitaxial Layer
CMP Oxide
Circa 1997
TiSi
TiSi
STI
P+ Substrate

50. CMOS VLSI Design
Why Changes?
CMP Oxide
Chemical Mechanical Polishing (CMP)
Flatten surface to enable multiple levels of metal
Tungsten (W) contacts and Vias
Enable use of CMP
P+ Substrate
Reduce substrate resistance and thus reduce latch-up.
P- Epi
Needed to enable p and n transistor tub doping with P+
Substrate
Shallow Trench Isolation (STI)
Reduce source and drain capacitance
Reduce source and drain spacing
Tungsten-Silicide
Reduce gate resistance
CMOS Processing Slide 50

51. CMOS VLSI Design
CMOS Processing Slide 51
Twin Tub CMOS w/STI & Al-W metal
n-poly
p-poly
metal (Al)
STI
P+ Substrate P+ Substrate
P- Epitaxial Layer
CMP Oxide
Deep Tub Implant
V
T
Adjust
(Shallow Implant)
WSi
WSi

52. CMOS VLSI Design
Dual Damascene Cu Process
CMOS Processing Slide 52

53. CMOS VLSI Design
TSMC 0.18 CMOS Cross Section
CMOS Processing Slide 53
Al Metal 1
Al Metal 2
Al Metal 3
W Contact
W Via 1
W Via 2
Drain
Shallow
Trench
Isolation
(STI)
Poly
Gate
Source
SiO
2

54. CMOS VLSI Design
130 nm transistor
CMOS Processing Slide 54
WSi
Poly Si Gate
Spacer
Source/Drain

55. CMOS VLSI Design
Deep Sub Micron Progress
CMOS Processing Slide 55
http://www.zdnet.com/blog/computers/why-intels-22nm-technology-really-matters/5703

56. CMOS VLSI Design
Intel 45 nm Transistor
CMOS Processing Slide 56
http://www.eetimes.com/design/automotive-design/4004782/Under-the-Hood-Intel-s-45-nm-high-k-metal-gate-process

57. CMOS VLSI Design
TriGateor FinFETTransistor
CMOS Processing Slide 57
http://www.electronicproducts.com/uploadedImages/Digital_ICs/Microprocessors_Microcontrollers_DSPs/MOUCM_Processing0102_AUG2013.jpg

58. CMOS VLSI Design
32 and 28 nm Transistors
CMOS Processing Slide 58
http://www.sciencedirect.com/science/article/pii/S0040609011018335

59. CMOS VLSI Design
Intel 22 nm Tri-gate Transistor
CMOS Processing Slide 59
http://www.electroiq.com/blogs/chipworks_real_chips_blog/2012/04/intel-s-22-nm-trigate-transistors-exposed.html

60. CMOS VLSI Design
10nm FINFET
CMOS Processing Slide 60
http://www.electronicproducts.com/uploadedImages/Digital_ICs/Microprocessors_Microcontrollers_DSPs/MOUCM_Processing0103_AUG2013.jpg

61. CMOS VLSI Design
A 10nm Protein Transistor
CMOS Processing Slide 61
http://www.nature.com/nnano/journal/v7/n3/fig_tab/nnano.2012.7_F2.html

62. CMOS VLSI Design
Carbon Nanotube Transistor
CMOS Processing Slide 62
http://www.infineon.com/export/sites/default/media/press/Image/migration/nanotube_english.jpg