CMOS VLSI Design.312313131312pp3213123213313123t

CMOS VLSIDigital Design Slide 1
CMOS VLSI Design
Digital Design

CMOS VLSIDigital Design Slide 2
Overview
Physical principles
Combinational logic
Sequential logic
Datapath
Memories
Trends

CMOS VLSIDigital Design Slide 3
Dopants
Silicon is a semiconductor
Pure silicon has no free carriers and conducts poorly
Adding dopants increases the conductivity
Group V: extra electron (n-type)
Group III: missing electron, called hole (p-type)
AsSiSi
SiSiSi
SiSiSi
B SiSi
SiSiSi
SiSiSi
-
+
+
-

CMOS VLSIDigital Design Slide 4
nMOS Operation
Body is commonly tied to ground (0 V)
When the gate is at a low voltage:
–P-type body is at low voltage
–Source-body and drain-body diodes are OFF
–No current flows, transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO
2
Polysilicon
n+
D
0
S

CMOS VLSIDigital Design Slide 5
Transistors as Switches
We can view MOS transistors as electrically
controlled switches
Voltage at gate controls path from source to drain
g
s
d
g = 0
s
d
g = 1
s
d
g
s
d
s
d
s
d
nMOS
pMOS
OFF
ON
ON
OFF

CMOS VLSIDigital Design Slide 6
CMOS Inverter
AY
0
1
V
DD
A Y
GND
A Y

CMOS VLSIDigital Design Slide 7
Inverter Cross-section
Typically use p-type substrate for nMOS transistors
Requires n-well for body of pMOS transistors
n+
p substrate
p+
n well
A
Y
GND V
DD
n+ p+
SiO
2
n+ diffusion
p+ diffusion
polysilicon
metal1
nMOS transistor pMOS transistor

CMOS VLSIDigital Design Slide 8
Inverter Mask Set
Transistors and wires are defined by masks
Cross-section taken along dashed line
GND V
DD
Y
A
substrate tap well tap
nMOS transistor pMOS transistor

CMOS VLSIDigital Design Slide 9
Fabrication Steps
Start with blank wafer
Build inverter from the bottom up
First step will be to form the n-well
–Cover wafer with protective layer of SiO
2
(oxide)
–Remove layer where n-well should be built
–Implant or diffuse n dopants into exposed wafer
–Strip off SiO
2
p substrate

CMOS VLSIDigital Design Slide 10
Oxidation
Grow SiO
2
on top of Si wafer
–900 – 1200 C with H
2O or O
2 in oxidation furnace
p substrate
SiO
2

CMOS VLSIDigital Design Slide 11
Photoresist
Spin on photoresist
–Photoresist is a light-sensitive organic polymer
–Softens where exposed to light
p substrate
SiO
2
Photoresist

CMOS VLSIDigital Design Slide 12
Lithography
Expose photoresist through n-well mask
Strip off exposed photoresist
p substrate
SiO
2
Photoresist

CMOS VLSIDigital Design Slide 13
Etch
Etch oxide with hydrofluoric acid (HF)
–Seeps through skin and eats bone; nasty stuff!!!
Only attacks oxide where resist has been exposed
p substrate
SiO
2
Photoresist

CMOS VLSIDigital Design Slide 14
Strip Photoresist
Strip off remaining photoresist
–Use mixture of acids called piranah etch
Necessary so resist doesn’t melt in next step
p substrate
SiO
2

CMOS VLSIDigital Design Slide 15
n-well
n-well is formed with diffusion or ion implantation
Diffusion
–Place wafer in furnace with arsenic gas
–Heat until As atoms diffuse into exposed Si
Ion Implanatation
–Blast wafer with beam of As ions
–Ions blocked by SiO
2, only enter exposed Si
n well
SiO
2

CMOS VLSIDigital Design Slide 16
Simplified Design Rules
Conservative rules to get you started

CMOS VLSIDigital Design Slide 17
Complementary CMOS
Complementary CMOS logic gates
–nMOS pull-down network
–pMOS pull-up network
–a.k.a. static CMOS
pMOS
pull-up
network
output
inputs
nMOS
pull-down
network
Pull-up OFFPull-up ON
Pull-down OFFZ (float) 1
Pull-down ON0 X (crowbar)

CMOS VLSIDigital Design Slide 18
Example: NAND3
Horizontal N-diffusion and p-diffusion strips
Vertical polysilicon gates
Metal1 V
DD
rail at top
Metal1 GND rail at bottom
32  by 40 

CMOS VLSIDigital Design Slide 19
I-V Characteristics
In Linear region, I
ds
depends on
–How much charge is in the channel?
–How fast is the charge moving?

CMOS VLSIDigital Design Slide 20
Channel Charge
MOS structure looks like parallel plate capacitor
while operating in inversion
–Gate – oxide – channel
Q
channel
= CV
C = C
g
= 
ox
WL/t
ox
= C
ox
WL
V = V
gc
– V
t
= (V
gs
– V
ds
/2) – V
t
n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator, 
ox
= 3.9)
polysilicon
gate
C
ox
= 
ox
/ t
ox

CMOS VLSIDigital Design Slide 21
Carrier velocity
Charge is carried by e-
Carrier velocity v proportional to lateral E-field
between source and drain
v = E  called mobility
E = V
ds
/L
Time for carrier to cross channel:
–t = L / v

CMOS VLSIDigital Design Slide 22
nMOS Linear I-V
Now we know
–How much charge Q
channel is in the channel
–How much time t each carrier takes to cross
channel
ox
2
2
ds
ds
gs t ds
ds
gs t ds
Q
I
t
W V
C V V V
L
V
V V V



 
   
 
 
   
 
ox
=
W
C
L
 

CMOS VLSIDigital Design Slide 23
Example
Example: a 0.6 m process from AMI semiconductor
–t
ox = 100 Å
–  = 350 cm
2
/V*s
–V
t
= 0.7 V
Plot I
ds
vs. V
ds
–V
gs = 0, 1, 2, 3, 4, 5
–Use W/L = 4/2 

14
2
8
3.9 8.85 10
350 120 /
100 10
ox
W W W
C A V
L L L
  


    
  
  
   
0 1 2 3 4 5
0
0.5
1
1.5
2
2.5
V
ds
I
d
s
(
m
A
)
V
gs
= 5
V
gs
= 4
V
gs
= 3
V
gs
= 2
V
gs
= 1

CMOS VLSIDigital Design Slide 24
Capacitance
Any two conductors separated by an insulator have
capacitance
Gate to channel capacitor is very important
–Creates channel charge necessary for operation
Source and drain have capacitance to body
–Across reverse-biased diodes
–Called diffusion capacitance because it is
associated with source/drain diffusion

CMOS VLSIDigital Design Slide 25
Gate Capacitance
Approximate channel as connected to source
C
gs = 
oxWL/t
ox = C
oxWL = C
permicronW
C
permicron
is typically about 2 fF/m
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator, 
ox
= 3.9
0
)
polysilicon
gate

CMOS VLSIDigital Design Slide 26
Diffusion Capacitance
C
sb
, C
db
Undesirable, called parasitic capacitance
Capacitance depends on area and perimeter
–Use small diffusion nodes
–Comparable to C
g
for contacted diff
–½ C
g
for uncontacted
–Varies with process

CMOS VLSIDigital Design Slide 27
RC Delay Model
Use equivalent circuits for MOS transistors
–Ideal switch + capacitance and ON resistance
–Unit nMOS has resistance R, capacitance C
–Unit pMOS has resistance 2R, capacitance C
Capacitance proportional to width
Resistance inversely proportional to width
kg
s
d
g
s
d
kC
kC
kC
R/k
kg
s
d
g
s
d
kC
kC
kC
2R/k

CMOS VLSIDigital Design Slide 28
Introduction
Chips are mostly made of wires called interconnect
–In stick diagram, wires set size
–Transistors are little things under the wires
–Many layers of wires
Wires are as important as transistors
–Speed
–Power
–Noise
Alternating layers run orthogonally

CMOS VLSIDigital Design Slide 29
Wire Capacitance
Wire has capacitance per unit length
–To neighbors
–To layers above and below
C
total
= C
top
+ C
bot
+ 2C
adj
layer n+1
layer n
layer n-1
C
adj
C
top
C
bot
ws
t
h
1
h
2

CMOS VLSIDigital Design Slide 30
Lumped Element Models
Wires are a distributed system
–Approximate with lumped element models
3-segment -model is accurate to 3% in simulation
L-model needs 100 segments for same accuracy!
Use single segment -model for Elmore delay
C
R
C/N
R/N
C/N
R/N
C/N
R/N
C/N
R/N
R
C
L-model
R
C/2C/2
R/2R/2
C
N segments
-model T-model

CMOS VLSIDigital Design Slide 31
Crosstalk
A capacitor does not like to change its voltage
instantaneously.
A wire has high capacitance to its neighbor.
–When the neighbor switches from 1-> 0 or 0->1,
the wire tends to switch too.
–Called capacitive coupling or crosstalk.
Crosstalk effects
–Noise on nonswitching wires
–Increased delay on switching wires

CMOS VLSIDigital Design Slide 32
Coupling Waveforms
Aggressor
Victim (undriven): 50%
Victim (half size driver): 16%
Victim (equal size driver): 8%
Victim (double size driver): 4%
t (ps)
0 200 400 600 800 1000 1200140018002000
0
0.3
0.6
0.9
1.2
1.5
1.8
Simulated coupling for C
adj
= C
victim

CMOS VLSIDigital Design Slide 33
Introduction
What makes a circuit fast?
–I = C dV/dt -> t
pd  (C/I) V
–low capacitance
–high current
–small swing
Logical effort is proportional to C/I
pMOS are the enemy!
–High capacitance for a given current
Can we take the pMOS capacitance off the input?
Various circuit families try to do this…
B
A
11
4
4
Y

CMOS VLSIDigital Design Slide 34
Pseudo-nMOS
In the old days, nMOS processes had no pMOS
–Instead, use pull-up transistor that is always ON
In CMOS, use a pMOS that is always ON
–Ratio issue
–Make pMOS about ¼ effective strength of
pulldown network
V
out
V
in
16/2
P/2
I
ds
load
0 0.30.60.91.21.51.8
0
0.3
0.6
0.9
1.2
1.5
1.8
P = 24
P = 4
P = 14
V
in
V
out

CMOS VLSIDigital Design Slide 35
Dynamic Logic
Dynamic gates uses a clocked pMOS pullup
Two modes: precharge and evaluate
1
2
A Y
4/3
2/3
A
Y
1
1
A
Y

Static Pseudo-nMOS Dynamic
 Precharge Evaluate
Y
Precharge

CMOS VLSIDigital Design Slide 36
Pass Transistor Circuits
Use pass transistors like switches to do logic
Inputs drive diffusion terminals as well as gates
CMOS + Transmission Gates:
–2-input multiplexer
–Gates should be restoring
A
B
S
S
S
Y
A
B
S
S
S
Y

CMOS VLSIDigital Design Slide 37
Sequencing
Combinational logic
–output depends on current inputs
Sequential logic
–output depends on current and previous inputs
–Requires separating previous, current, future
–Called state or tokens
–Ex: FSM, pipeline
CL
clk
in out
clk clk clk
CL CL
PipelineFinite State Machine

CMOS VLSIDigital Design Slide 38
Sequencing Overhead
Use flip-flops to delay fast tokens so they move
through exactly one stage each cycle.
Inevitably adds some delay to the slow tokens
Makes circuit slower than just the logic delay
–Called sequencing overhead
Some people call this clocking overhead
–But it applies to asynchronous circuits too
–Inevitable side effect of maintaining sequence

CMOS VLSIDigital Design Slide 39
Sequencing Elements
Latch: Level sensitive
–a.k.a. transparent latch, D latch
Flip-flop: edge triggered
–A.k.a. master-slave flip-flop, D flip-flop, D register
Timing Diagrams
–Transparent
–Opaque
–Edge-trigger
D
F
lo
p
L
a
t
c
h
Q
clk clk
D Q
clk
D
Q (latch)
Q (flop)

CMOS VLSIDigital Design Slide 40
Latch Design
Buffered output
+No backdriving
Widely used in standard cells
+ Very robust (most important)
-Rather large
-Rather slow (1.5 – 2 FO4 delays)
-High clock loading


Q
D
X



CMOS VLSIDigital Design Slide 41
Sequencing Methods
Flip-flops
2-Phase Latches
Pulsed Latches
F
lip
-
F
lo
p
s
F
lo
p
L
a
t
c
h
F
lo
p
clk

1

2

p
clk clk
L
a
t
c
h
L
a
t
c
h

p

p

1

1

2
2
-
P
h
a
s
e

T
r
a
n
s
p
a
r
e
n
t

L
a
t
c
h
e
s
P
u
ls
e
d

L
a
t
c
h
e
s
Combinational Logic
Combinational
Logic
Combinational
Logic
Combinational Logic
L
a
t
c
h
L
a
t
c
h
T
c
T
c
/2
t
nonoverlap
t
nonoverlap
t
pw
Half-Cycle 1 Half-Cycle 1

CMOS VLSIDigital Design Slide 42
Summary
Flip-Flops:
–Very easy to use, supported by all tools
2-Phase Transparent Latches:
–Lots of skew tolerance and time borrowing
Pulsed Latches:
–Fast, some skew tol & borrow, hold time risk

CMOS VLSIDigital Design Slide 43
Full Adder Design I
Brute force implementation from eqns
out
( , , )
S A B C
C MAJ A B C
  

A
B
C
S
C
out
M
A
J
A
B
C
A
B B
B
A
C
S
C
CC
B B
B
A A
A B
C
B
A
CBA A B C
C
out
C
A
A
BB

CMOS VLSIDigital Design Slide 44
Carry-Skip Adder
Carry-ripple is slow through all N stages
Carry-skip allows carry to skip over groups of n bits
–Decision based on n-bit propagate signal
C
in
+
S
4:1
P
4:1
A
4:1
B
4:1
+
S
8:5
P
8:5
A
8:5
B
8:5
+
S
12:9
P
12:9
A
12:9
B
12:9
+
S
16:13
P
16:13
A
16:13
B
16:13
C
out
C
4
1
0
C
8
1
0
C
12
1
0
1
0

CMOS VLSIDigital Design Slide 45
Tree Adder
If lookahead is good, lookahead across lookahead!
–Recursive lookahead gives O(log N) delay
Many variations on tree adders

CMOS VLSIDigital Design Slide 46
Memory Arrays
Memory Arrays
Random Access Memory Serial Access MemoryContent Addressable Memory
(CAM)
Read/Write Memory
(RAM)
(Volatile)
Read Only Memory
(ROM)
(Nonvolatile)
Static RAM
(SRAM)
Dynamic RAM
(DRAM)
Shift Registers Queues
First In
First Out
(FIFO)
Last In
First Out
(LIFO)
Serial In
Parallel Out
(SIPO)
Parallel In
Serial Out
(PISO)
Mask ROM Programmable
ROM
(PROM)
Erasable
Programmable
ROM
(EPROM)
Electrically
Erasable
Programmable
ROM
(EEPROM)
Flash ROM

CMOS VLSIDigital Design Slide 47
Array Architecture
2
n
words of 2
m
bits each
If n >> m, fold by 2
k
into fewer rows of more columns
Good regularity – easy to design
Very high density if good cells are used
r
o
w

d
e
c
o
d
e
r
column
decoder
n
n-k
k
2
m
bits
column
circuitry
bitline conditioning
memory cells:
2
n-k
rows x
2
m+k
columns
bitlines
wordlines

CMOS VLSIDigital Design Slide 48
6T SRAM Cell
Cell size accounts for most of array size
–Reduce cell size at expense of complexity
6T SRAM Cell
–Used in most commercial chips
–Data stored in cross-coupled inverters
Read:
–Precharge bit, bit_b
–Raise wordline
Write:
–Drive data onto bit, bit_b
–Raise wordline
bit bit_b
word

CMOS VLSIDigital Design Slide 49
SRAM Sizing
High bitlines must not overpower inverters during
reads
But low bitlines must write new value into cell
bit bit_b
med
A
weak
strong
med
A_b
word

CMOS VLSIDigital Design Slide 50
Decoders
n:2
n
decoder consists of 2
n
n-input AND gates
–One needed for each row of memory
–Build AND from NAND or NOR gates
Static CMOS Pseudo-nMOS
word0
word1
word2
word3
A0A1
A1
word
A0
11
1/2
2
4
8
16
word
A0
A1
1
1
11
4
8word0
word1
word2
word3
A0A1

CMOS VLSIDigital Design Slide 51
Decoder Layout
Decoders must be pitch-matched to SRAM cell
–Requires very skinny gates
GND
VDD
word
buffer inverterNAND gate
A0A0A1A2A3 A2A3 A1

CMOS VLSIDigital Design Slide 52
Sense Amplifiers
Bitlines have many cells attached
–Ex: 32-kbit SRAM has 256 rows x 128 cols
–128 cells on each bitline
t
pd
 (C/I) V
–Even with shared diffusion contacts, 64C of
diffusion capacitance (big C)
–Discharged slowly through small transistors
(small I)
Sense amplifiers are triggered on small voltage
swing (reduce V)

CMOS VLSIDigital Design Slide 53
Queues
Queues allow data to be read and written at different
rates.
Read and write each use their own clock, data
Queue indicates whether it is full or empty
Build with SRAM and read/write counters (pointers)
Queue
WriteClk
WriteData
FULL
ReadClk
ReadData
EMPTY

CMOS VLSIDigital Design Slide 54
CAMs
Extension of ordinary memory (e.g. SRAM)
–Read and write memory as usual
–Also match to see which words contain a key
CAM
adrdata/key
match
read
write

CMOS VLSIDigital Design Slide 55
10T CAM Cell
Add four match transistors to 6T SRAM
–56 x 43  unit cell
bit bit_b
word
match
c
e
ll
c
e
ll_
b

CMOS VLSIDigital Design Slide 56
CAM Cell Operation
Read and write like ordinary SRAM
For matching:
–Leave wordline low
–Precharge matchlines
–Place key on bitlines
–Matchlines evaluate
Miss line
–Pseudo-nMOS NOR of match lines
–Goes high if no words match
r
o
w

d
e
c
o
d
e
r
weak
miss
match0
match1
match2
match3
clk
column circuitry
CAM cell
address
data
read/write

CMOS VLSIDigital Design Slide 57
ROM Example
4-word x 6-bit ROM
–Represented with dot diagram
–Dots indicate 1’s in ROM
Word 0: 010101
Word 1: 011001
Word 2: 100101
Word 3: 101010
ROM Array
2:4
DEC
A0A1
Y0Y1Y2Y3Y4Y5
weak
pseudo-nMOS
pullups
Looks like 6 4-input pseudo-nMOS NORs

CMOS VLSIDigital Design Slide 58
PLAs
A Programmable Logic Array performs any function
in sum-of-products form.
Literals: inputs & complements
Products / Minterms: AND of literals
Outputs: OR of Minterms
Example: Full Adder
out
s abc abc abc abc
c ab bc ac
   
  
AND Plane OR Plane
abc
abc
abc
abc
ab
bc
ac
sa b c
out
c
M
in
t
e
r
m
s
Inputs Outputs

CMOS VLSIDigital Design Slide 59
PLA Schematic & Layout
AND Plane OR Plane
abc
abc
abc
abc
ab
bc
ac
s
a b c
out
c

CMOS VLSIDigital Design Slide 60
Ideal nMOS I-V Plot
180 nm TSMC process
Ideal Models
–  = 155(W/L) A/V
2
– V
t = 0.4 V
– V
DD
= 1.8 V
I
ds
(A)
V
ds
0 0.30.60.91.21.51.8
100
200
300
400
V
gs
= 0.6
V
gs
= 0.9
V
gs
= 1.2
V
gs
= 1.5
V
gs
= 1.8
0

CMOS VLSIDigital Design Slide 61
Simulated nMOS I-V Plot
180 nm TSMC process
BSIM 3v3 SPICE models
What differs?
–Less ON current
–No square law
–Current increases
in saturation
V
ds
0 0.30.60.91.2 1.5
V
gs
= 1.8
I
ds
(A)
0
50
100
150
200
250
V
gs
= 1.5
V
gs
= 1.2
V
gs
= 0.9
V
gs
= 0.6

CMOS VLSIDigital Design Slide 62
Velocity Saturation
We assumed carrier velocity is proportional to E-field
–v = E
lat = V
ds/L
At high fields, this ceases to be true
–Carriers scatter off atoms
–Velocity reaches v
sat
•Electrons: 6-10 x 10
6
cm/s
•Holes: 4-8 x 10
6
cm/s
–Better model
E
sat0
0
slope = 
E
lat

2E
sat
3E
sat

sat

sat
/ 2
lat
sat sat
lat
sat
μ
μ
1
E
v v E
E
E
  


CMOS VLSIDigital Design Slide 63
Channel Length Modulation
Reverse-biased p-n junctions form a depletion region
–Region between n and p with no carriers
–Width of depletion L
d
region grows with reverse bias
–L
eff
= L – L
d
Shorter L
eff
gives more current
–I
ds increases with V
ds
–Even in saturation
n+
p
GateSource Drain
bulk Si
n+
V
DDGND
V
DD
GND
L
L
eff
Depletion Region
Width: L
d

CMOS VLSIDigital Design Slide 64
Body Effect
V
t
: gate voltage necessary to invert channel
Increases if source voltage increases because
source is connected to the channel
Increase in V
t
with V
s
is called the body effect

CMOS VLSIDigital Design Slide 65
OFF Transistor Behavior
What about current in cutoff?
Simulated results
What differs?
–Current doesn’t go
to 0 in cutoff
V
t
Sub-
threshold
Slope
Sub-
threshold
Region
Saturation
Region
V
ds
= 1.8
I
ds
V
gs
0 0.3 0.60.91.21.51.8
10 pA
100 pA
1 nA
10 nA
100 nA
1 A
10 A
100 A
1 mA

CMOS VLSIDigital Design Slide 66
Leakage Sources
Subthreshold conduction
–Transistors can’t abruptly turn ON or OFF
Junction leakage
–Reverse-biased PN junction diode current
Gate leakage
–Tunneling through ultrathin gate dielectric
Subthreshold leakage is the biggest source in
modern transistors

CMOS VLSIDigital Design Slide 67
Low Power Design
Reduce dynamic power
– : clock gating, sleep mode
–C: small transistors (esp. on clock), short wires
–V
DD
: lowest suitable voltage
–f: lowest suitable frequency
Reduce static power
–Selectively use ratioed circuits
–Selectively use low V
t devices
–Leakage reduction:
stacked devices, body bias, low temperature

CMOS VLSIDigital Design Slide 68
Chip-to-Package Bonding
Traditionally, chip is surrounded by pad frame
–Metal pads on 100 – 200 m pitch
–Gold bond wires attach pads to package
–Lead frame distributes signals in package
–Metal heat spreader helps with cooling

CMOS VLSIDigital Design Slide 69
Bidirectional Pads
Combine input and output pad
Need tristate driver on output
–Use enable signal to set direction
–Optimized tristate avoids huge series transistors
PAD
Din
Dout
En
Dout
En Y
Dout
NAND
NOR

CMOS VLSIDigital Design Slide 70
Device Scaling

CMOS VLSIDigital Design Slide 71
Interconnect Delay