CO Lehhdndkdbbdkdcture1_Introduction .pdf

Computer Organisation

1. PCC-CS 302
(Professional Core Courses)
Computer Organization
Lecture 1
Introduction
TAPAN CHOWDHURY

2. Course Outcome
CS302.1
ModelabasicCPUwithgivenspecificationsof
IASalongwithitsperformancemetrics
CS302.2
Illustrateandmakeuseoftheoperationsofan
ALU.
CS302.3
Analyzetheperformanceofmemoryhierarchy
basedondifferentperformancemetrics
CS302.4
ContrastCISCwithRISCwhileestablishing
significanceofinstructionpipelining
CS302.5
OutlinetheperformanceofcontrolunitandI/O
unit

3. A Brief History of Computers
The Abacus
3000BC
Charles Babbage’s Difference Engine 1823

4. A Brief History of Computers
ENIAC (Electronic Numerical Integrator and
Computer)
Designed by Mauchly and Eckert
University of Pennsylvania
First general-purpose electronic digital computer
Response to WW2 need to calculate trajectory
tables for weapons.
Built 1943-1946 –too late for war effort.
ENIAC DetailsDecimal (not binary)
20 accumulators of 10 digits
Programmed manually by switches
18,000 vacuum tubes
30 tons
15,000 square feet
140 kW power consumption
5,000 additions per second
Vacuum Tube

6. Von Neumann Machine
Stored Program Concept
Main memory storing programs
and data
ALU operating on binary data
Control unit interpreting
instructions from memory and
executing
Input and output equipment
operated by control unit
Princeton Institute for Advanced
Studies (IAS).
Completed 1952
Dr. Von Neuman with the IAS computer

7. Structure of Von Neumann Machine

8. CPU + memory
memory
CPU
PC
address
data
IRADD r5,r1,r3
200
200
ADD r5,r1,r3

9. Memory of the IAS
1000 storage locations called words.
Each word 40 bits.
A word may contain:
A numbers stored as 40 binary digits (bits).
An instruction-pair. Each instruction:
An opcode (8 bits)
An address (12 bits) –designating one of the 1000 words in memory.

10. Von Neumann / IAS Machine Registers
MBR: Memory Buffer Register
-contains the word to be stored in
memory or just received from memory.
MAR: Memory Address Register
-specifies the address in memory of
the word to be stored or retrieved into
MBR.
IR: Instruction Register -contains the
8-bit opcode currently being executed.
IBR: Instruction Buffer Register
-temporary store for RHS instruction
from word in memory.
PC: Program Counter -address of
next instruction-pair to fetch from
memory.
AC: Accumulator & MQ: Multiplier
quotient -holds operands and results
of ALU ops.
AC MQ
MBR
IBR PC
IR MAR

11. Start
Is next
instruction
in IBR?
MAR PC
MBRM(MAR)
IR IBR(0:7)
MAR IBR(8:19)
IR MBR(20:27)
MAR MBR(28:39)
Left
instruction
required?
IBR MBR(20:39)
IR MBR(0:7)
MAR MBR(8:19)
PC PC + 1
FETCH CYCLE
No memory
access
required
Yes No
No Yes
Execution Cycle
EXECUTION CYCLE

12. Is next
instruction
in IBR?
MAR PC
MBRM(MAR)
IR IBR(0:7)
MAR IBR(8:19)
IR MBR(20:27)
MAR MBR(28:39)
Left
instruction
required?
IBR MBR(20:39)
IR MBR(0:7)
MAR MBR(8:19)
PC PC + 1
No memory
access
required
Yes No
No Yes
MEMORY
1.LOAD M(X) 500, ADD M(X) 501
2.STOR M(X) 500, (Other Ins)
.....
500.3
501.4
FETCH CYCLE
PC
MBR
IR
IBR
MAR
1
1
LOAD M(X) 500, ADD M(X) 501
AC
ADD M(X) 501
LOAD M(X)
500
3
ADD M(X)
501
2
7
2
STOR M(X) 500, (Other Ins)
(Other Ins)
STOR M(X)
500

13. Flowchart of IAS Operation

14. Harvard architecture
CPU
PC
data memory
program memory
address
data
address
data

15. The Harvard Architecture (1)
•Harvard architectureis a computer architecture with
physically separate storage and signal pathways for
instructions and data.
•The term originated from the Harvard Mark I relay-based
computer, which stored instructions on punched tape (24
bits wide) and data in electro-mechanical counters (23
digits wide). These early machines had limited data
storage, entirely contained within the data processing unit,
and provided no access to the instruction storage as data,
making loading and modifying programs an entirely
offline process.

16. The Harvard Architecture (2)
•In a computer with a Von Neumann architecture (and no
cache), the CPU can be either reading an instruction or
reading/writing data from/to the memory.
–Both cannot occur at the same time since the instructions
and data use the same bus system.
•In a computer using the Harvard architecture, the CPU can
read both an instruction and perform a data memory access
at the same time, even without a cache.
•A Harvard architecture computer can thus be faster for a
given circuit complexity because instruction fetches and
data access do not contend for a single memory pathway.

17. The Harvard Architecture (3)
•In a Harvard architecture, there is no need to make the two
memories share characteristics. In particular, the word width,
timing, implementation technology, and memory address
structure can differ.
•In some systems, instructions can be stored in read-only
memory while data memory generally requires read-write
memory.
•Instruction memory is often wider than data memory.

18. Von Neumann and Harvard architectures
•Von Neumann
–Allows instructions and data to be mixed and stored in the same
memory module
–More flexible and easier to implement
–Suitable for most of the general purpose processors
•Harvard:
–Uses separate memory modules for instructions and for data
–It is easier to pipeline
–Higher memory throughput
–Suitable for DSP (Digital Signal Processors)

19. 2
nd
Generation: Transistor Based Computers
Transistors replaced
vacuum tubes
Smaller
Cheaper
Less heat dissipation
Solid State device
Made from Silicon (Sand)
Invented 1947 at Bell Labs
William Shockley et al.
Commercial Transistor based
computers:
NCR & RCA produced
small transistor machines
IBM 7000
DEC –1957 (PDP-1)
First transistor computer –Manchester University 1953.

20. 3
rd
Generation: Integrated Circuits
A single, self-contained transistor is called a discrete component.
Transistor based computers –discrete components manufactured
separately, packaged in their
own containers, and soldered
or wired together onto circuit
boards.
Early 2
nd
generation
computers contained
about 10,000
transistors –but grew to
hundreds of thousands!!!!
(Manufacturing nightmare).
Integrated circuits
revolutionized electronics.
Silicon Chip –Collection of tiny transistors

21. Generations of Computers
Vacuum tube -1946-1957 (One bit Size of a hand)
Transistor -1958-1964 (One bit Size of a fingernail)
Small scale integration -1965 on
Up to 100 devices on a chip
•Medium scale integration -to 1971
100-3,000 devices on a chip
•Large scale integration -1971-1977
3,000 -100,000 devices on a chip
•Very large scale integration -1978 to date
100,000 -100,000,000 devices on a chip
•Ultra large scale integration
Over 100,000,000 devices on a chip
Thousands of bits
on the size of a
hand
Millions of bits
on the size of a
fingernail.

22. Moore’s Law
Moore observed that the number of transistors per chip DOUBLED each
year.
Predicted the pace would continue.
Since 1975 double every 18 months.
The cost of a chip almost
unchanged. cost of logic
and memory decreased.
Logic and memory
elements moved closer
together. SPEED.
Computer becomes
smaller. more uses.
Reduction in power
and cooling requirements.
Interconnections on IC
more reliable than
soldered connections.
Fewer interchip connections.

23. Amdahl’s Law
The performance to be gained from using some faster mode of execution is
limited by the fraction of the time the faster mode can be used.
Speedup = Execution time for entire task without using the enhancement
Execution time for the entire task using the enhancement when possible.
We need to know two critical factors:
1.The fraction of the computation timein the original machine that
can be converted to take advantage of the enhancement.
Fraction
enhanced= Enhanced time
Non enhanced time
If a program takes 60 seconds to execute and 20 seconds can be
enhanced –then fraction
enhanced= 20/60.
2.The improvement gainedby the enhanced execution mode.
How much faster will the task run if the enhanced mode were used for
the entire program?
Speedup
enhanced = Time of original mode
Time of enhanced mode

24. Amdahl’s Law
The execution time using the original machine with the enhanced mode
will be the time spent using the unenhanced portion of the machine plus
the time spent using the enhancement.
Original Execution time100 seconds
60 seconds
not enhanced
40 seconds
can be enhanced
60 seconds
not enhanced
20 secs
after
enhance
Execution time
following enhancement
Speedup
enhanced= Time of original mode = 100= 1.25
Time of enhanced mode 80

25. Amdahl’s Law
Execution time
new= Execution time
old* (1 –Fraction
enhanced+
Fraction
enhanced
Speedup
enhanced
100 seconds
60 seconds
not enhanced
40 seconds
can be enhanced
60 seconds
not enhanced
20 secs
after
enhance
Execution time
new= 100 * (1 –0.4 +
= (100 * 0.6) + (100 * (0.4 / 2))
= 60 + 20
= 80 seconds
Speedup
overall= 100/80 = 1.25
0.4
(40/20)

26. Amdahl’s Law
Speedup
overall= =
Execution time
old
Execution time
new
1
(1 –Fraction
enhanced+
Fraction
enhanced
Speedup
enhanced
Example # 1: (Hennessy & Patterson page 30)
•Suppose we were considering an enhancement that runs 10 times
faster than the original machine, but is only usable 40% of the
time.
•What is the overall speedup gained by incorporating the
enhancement?

27. Computer Components –Top Level View
PC = Program Counter
IR = Instruction Register
MAR = Memory Address
Register
MBR = Memory Buffer
Register
I/O AR = I/O Address
Register
I/O BR = I/O Buffer
Register

28. Basic Function
Basic function is executing a set of instructions stored in memory.
The processor fetchesinstructions from memory one at a time and executes
each instruction.
Program execution therefore consists of repeatedly fetching and executing
instructions.
The processing of a single instruction is called the instruction cycle.
The instruction cycleconsists of the fetch cycleand the execute cycle.

29. A Hypothetical Machine
Single data register (AC)
Instructions and data are 16
bits long.
Memory organized as 16 bit
words.
Instruction format provides:
4 bits for the opcode
2
4
= 16 different
opcodes.
12 bits for memory
address
2
12
= 4096 (4K) words
of memory directly
addressable.

30. The Processor -Instruction Cycles
•The instruction cycle is the procedure of processing an
instruction by the microprocessor:
–Fetches or reads the instruction from the memory
–Decodes the instruction, determining which instruction is to be
executed (which instruction has been fetched)
–Executes the instruction –performs the operations necessary to
complete what the instruction is suppose to do (different from
instruction to instruction, may read data from memory, may write
data to memory or I/O device, perform only operations within CPU
or combination of those)
•Each of the functions fetch -> decode -> execute consist of a
sequence of one or more operations inside the CPU (and
interaction with the subsystems)

31. Instruction address calculation (iac):Determine address of next instruction.
Instruction fetch (if):Read instruction from memory into the processor.
Instruction operation decoding (iod): Analyze instruction to determine type
of operation and operand(s) to use.
Operand address calculation (oac):If the operation involves referencing an
operand in memory or via I/O –determine the address of the operand.
Operand fetch:Fetch operand from memory or read it from I/O.
Data operation (do): Perform the operation in the instruction.
Operand store (os):Write the result to memory or I/O
Instruction
Cycle
State
Diagram

32. QUESTIONS ?
1.Explain Von Neumann or IAS Architecture.
2.What is Von Neumann bottleneck? How can this be reduced?
3.Describe the function of Major Components of a digital computer with neat
sketch.
4.What is Harvard Architecture? Explain using Block Diagram.
5.How does Harvard architecture differ from Von Neumann architecture?
6.What is an operating System? Briefly describe the major functions or roles of
Operating System?
7.Explain the types of operating System.
8.Explain the layers in computer system.
9.Differentiate between Compiler and Interpreter.