Combinational logic-style1_CMOS for VLSI

CMOS logic

1. Combinational Logic Gates in CMOS
References:
Adapted from: Digital Integrated Circuits: A Design
Perspective, J. Rabaey, Prentice Hall © UCB
Principles of CMOS VLSI Design: A Systems Perspective,
N. H. E. Weste, K. Eshraghian, Addison Wesley
Adapted from: EE216A Lecture Notes by Prof. K. Bult ©
UCLA

2. Combinational vs. Sequential Logic Combinational
Sequential
State
Out = f(In)Out = f(In, State)
State is related to previous inputs
Stored in registers, memory etc

3. Overview
• Static CMOS
– Complementary CMOS
– Ratioed Logic
– Pass Transistor/Transmission Gate Logic
• Dynamic CMOS Logic
–Domino
– np-CMOS

4. Static CMOS Circuit
• At every point in time (except during the switching
transients) each gate output is connected to either
V
DD
or V
SS
via a low-resistive path
• The outputs of the gates assume at all times the
value of the Boolean function, implemented by the
circuit
• In contrast, a dynamic circuit relies on temporary
storage of signal values on the capacitance of high
impedance circuit nodes

5. Digital Gates
Fundamental Parameters
• Area and Complexity
• Performance
• Power Consumption
• Robustness and Reliability

6. What Can Go Wrong in CMOS Logic?
• Incorrect or insufficient power supplies
• Power supply noise
• Noise on gate input
• Faulty connections between transistors
• Clock frequency too high or circuit too slow
Complementary CMOS is pretty
safe against these

7. How about Ratioed or Dynamic Logic?
• All the previous and
• Incorrect ratios in ratioed logic
• Charge sharing in dynamic logic
• Incorrect clocking in dynamic logic

8. Complementary CMOS
PUN PDN
in1
in2
in3
in1
in2
in3
V
DD
V
SS
F = G
NMOS only
PMOS only
PUN and PDN are dual networks

9. NMOS Transistors in Series/Parallel Connection • Transistors can be thought as a switch controlled by
its gate signal
• NMOS switch closes when switch control input is
high
XY
AB
X = Y if A = 1 and B = 1, i.e., AB = 1
• NMOS passes a strong 0 but a weak 1
XY
A
B
X = Y if A = 1 or B = 1, i.e., A + B = 1

10. NMOS Transistors in Series/Parallel Connection • Connect Y to GND
XY
AB
X = 0 if A = 1 and B = 1, i.e., A.B = 1
• Implement the complement of PDN
XY
A
B
X = 0 if A = 1 or B = 1, i.e., A + B = 1
X = A.B
X = A + B

11. PMOS Transistors in Series/Parallel Connection • PMOS switch closes when switch control input is low
XY
ABX = Y if A = 0 and B = 0
or A + B = 1
or A.B = 1
• PMOS passes a strong 1 but a weak 0
XY
A
B
X = Y if A = 0 or B = 0
A.B = 1
A + B = 1

12. PMOS Transistors in Series/Parallel Connection
• Connect Y to VDD
XY
AB
X = 1 if A = 0 and B = 0
• Combine series PDN and parallel PUN or parallel
PDN and series PUN to complete the logic design to
output good 1 and 0
XY
A
B
X = 1 if A = 0 or B = 0 X = A + B = A.B X = A.B = A + B

13. Complementary CMOS Logic Style Construction
• PUN is the DUAL of PDN (can be shown using
DeMorgan’s Theorems)
BA B A
=
+
B A AB
+
=
• The complementary gate is inverting
– Implements NAND, NOR, …
– Non-inverting boolean function needs an inverter
,...) , ,( ,...) , ,(
3 2 1 3 2 1
in in in F in in in G≡
≡

14. The NAND Circuit
B
A
B
A
+
11
10
01
0
1
A
B
B
Out
A
BA.
,...) , ,( ,...) , ,(
3 2 1 3 2 1
in in in F in in in G≡
BA G. : GND to connected PDN=
AB B A F V
DD
= + =: to connected PUN

15. B
A
10
00
01
0
1
A
B
AB
The NOR Circuit
A + B
A . B
B A+ = Output

16. Example Gate: COMPLEX CMOS GATE
V
DD
A
B
C
D
D
A
BC
OUT = D + A• (B+C)

17. F = ((A.B) + C.(A+B)) = carry
B
C
A
A
output
A
B
B
B
C
A
A
B
B
output
A
B
C
A
B A
C
Symmetrical !
Remove
redundancy

18. F = (ABC+ABC+ABC+ABC) = sum A -B
-A B
-C
-A -B
A B
C
C
-C
B A
-B -A
-B A
B
-A
output

19. Full Adder Circuit
A B
B
C
A
B
C
B
A
A
A
B
C
A
A
B
C
B C
C B A
-sum
-carry

20. 4-input NAND Gate
In1 In2 In3 In4
V
DD
GND
Out
ln2
ln1
ln2
Out
ln1
ln4
ln3
ln4 ln3

21. Standard Cell Layout Methodology
V
DD
V
SS
Well
signals
Routing Channel
metal1
polysilicon

22. Two Versions of (a+b).c
ac b ab c
x
x
GND
V
DD
V
DD
GND
(a) Input order {a c b}(b) Input order {a b c}

23. Logic Graph
V
DD
c
a
x
b
c
a
b
GND
x
V
DD
x
c
ba
i
j
i
j
PDN
PUN

24. Consistent Euler Path
{a b c}

25. Example: x = ab+cd
GND
x
a
bc
d
V
DD
x
GND
x
a
bc
d
V
DD
x
(a) Logic graphs for (
ab+cd
)
(b) Euler Paths {a b c d}
acd
x
V
DD
GND
(c) stick diagram for ordering {a b c d}
b

26. Properties of Complementary CMOS Gates
• High noise margin
–V
OH
and V
OL
are at V
DD
and G
ND
, respectively
• No static power consumption
– In steady state, no direct path between V
DD
and V
SS
• Comparable rise and fall times under appropriate
scaling of PMOS and NMOS transistors

27. Transistor Sizing
• For symmetrical response (dc, ac)
• For performance
• Input dependent
• Focus on worst-case

28. Propagation Delay Analysis -The Switch Model

29. Analysis of Propagation Delay
• Assume C
L
dominates
• Assume R
n
= R
p
= resistance
of minimum sized NMOS
inverter
•For t
pLH
– Worst case when only one
PMOS pulls up the output node
–t
pLH
∝R
p
C
L
•For t
pHL
– Worst case when two NMOS in
series
–t
pHL
∝2R
n
C
L

30. 3-Input NAND Gate
in
c
out
in
b
in
a
rise-time: 1 transistor (simple)
fall-time: 3 transistor in series
for linear approximation: take 3xR
on

31. 3-Input NAND Gate
in
c
out
in
b
in
a
If µ
n
= 3µ
p
for equal fall and rise time:
Take W
n
= W
p
If µ
n
= 2µ
p
for equal fall and rise time:
Take W
n
= (3/2)W
p

32. Design for Worst Case

33. 3-input NAND Gate with Parasitic Capacitors
in
c
out
in
b
in
a
C
p+load
C
a
C
b
C
c
P1P2P3
N3
N2
N1

34. Worst Case Approximation
Using Lumped RC Model
)) ( () (
3 2 1load p c b a N N N
pulldown pulldown df
C C C C R R R
C R t
+
+ + + × + + =
∑
×
∑=
(We ignore the constant term 0.69 or 1.22)

35. Penfield-Rubenstein Model
(Elmore Delay Model)
t
d
= Σ R
iC
i
with: C
i
= capacitance at node i
R
i
= total resistance between C
i
and supply
t
df
= [R
N1
C
a
] + [(R
N1
+ R
N2
)C
b
] +
[(R
N1
+ R
N2
+ R
N3
)(C
c
+ C
p+load
)]

36. Distributed RC Effects
CCCC
C
R
RRRR
2
.
2
)1 (nC nR nn RC
t
n
≈
+
×
=
Worst case under lumped model: t
n
= nR.nC

37. Comparison
t
df
= [R
NI
C
a
] + [(R
N1
+R
N2
)C
b
] + [(R
N1
+R
N2
+R
N3
)C
c
] +
[(R
N1
+ R
N2
+ R
N3
)C
p+load
]
R
N
C n(n+1)/2 + [(R
N1
+R
N2
+R
N3
)C
p+load
]
With R
N1
= R
N2
= R
N3
= R
N
and C
a
= C
b
= C
c
= C
n transistors in series RP-Model
Lumped-Model
R
N
C n
2
+ [(R
N1
+R
N2
+R
N3
)C
p+load
]

38. Macro Modeling
t
d
= [R
N1
C
a
] + [(R
N1
+R
N2
)C
b
] + [(R
N1
+ R
N2
+ R
N3
)C
c
] +
[(R
N1
+ R
N2
+ R
N3
)C
p
+ [(R
N1
+ R
N2
+ R
N3
)C
load
]
Internal delay
External load
t
d
= T
d, internal
+ λ x C
load

39. Effect of Loading
C
L
= 0.0pF
C
L
= 0.5pF
C
L
= 1.0pF
t
t
d
= t
d, internal
+ λx C
load

40. Effect of Fan-In and Fan-Out
on Delay
ln2
ln1
ln2
Out
ln1
ln4
ln3
ln4 ln3
• Fan-out: number of gates connected
– 2 gate capacitance per fan-out
• Fan-in: number of inputs to a gate
– Quadratic effect due to increasing
resistance and capacitance
FOa FIa FIa t
d3
2
2 1
+ + =

41. t
p
as a function of Fan-In
13579
fan-in
0.0
1.0
2.0
3.0
4.0
t
p
(nsec)
t
pHL
t
p
t
pLH
linear
quadratic
AVOID LARGE FAN-IN GATES! (Typically not more than FI < 4)

42. Example
3-Input NAND gate with Parasitic Capacitors
in
c
out
in
b
in
a
C
p+load
C
a
C
b
C
c
P1P2
P3
R
n
=0.5R
p
=
C
a
=C
b
=C
c
=C
j=0.05pF
C
p
=3C
j=0.15pF
C
load
=2C
g
=0.20pF
4
10 2
1
−
×

43. Worst Case Approximation
by Lumped Model
t
dr
= R
p
x (C
c
+C
p+load
) = 10000 x 0.4×10
-12
= 4.0ns
t
df
= ΣR
pulldown
x ΣC
pulldown
= (R
N1
+ R
N2
+ R
N3
) x (C
a
+ C
b
+ (C
c
+ C
p+load
))
= (3 x 5000) x (3 x 0.05 + 0.15 + 0.20) x 10
-12
= 7.5ns

44. Penfield-Rubenstein Model
t
dr
=R
p
x (C
c
+C
p+load
) = 10000 x 0.4×10
-12
= 4.0ns
t
df
= [R
N1
C
a
] + [(R
N1
+ R
N2
)C
b
] + [(R
N1
+ R
N2
+ R
N3
)(C
c
+ C
p+load
)]
= 5000 x 0.05pF + 10000 x 0.05pF + 15000 x 0.4pF = 6.75ns

45. Worst Case Approximation
by Lumped Model
t
dr
= R
p
x (C
c
+C
p+load
) = 10000 x 0.45×10
-12
= 4.5ns
t
df
= ΣR
pulldown
x ΣC
pulldown
= (R
N1
+ R
N2
+ R
N3
) x (C
a
+ C
b
+ (C
c
+ C
p+load
))
= (3 x 2500) x (3 x 0.10 + 0.15 + 0.20) x 10
-12
= 4.875ns
Make W
n
= 2W
p

46. Penfield-Rubenstein Model
t
dr
=R
p
x (C
c
+C
p+load
) = 10000 x 0.45×10
-12
= 4.5ns
t
df
= [R
N1
C
a
] + [(R
N1
+ R
N2
)C
b
] + [(R
N1
+ R
N2
+ R
N3
)(C
c
+ C
p+load
)]
= 2500 x 0.10pF + 5000 x 0.10pF + 7500 x 0.45pF = 4.125ns
Make W
n
= 2W
p

47. RewritingPenfield-Rubenstein Equation
t
d
= Σ R
ii
C
downstream-i
with: C
downstream-i
= downstream capacitance at node i
R
ii
= resistance at node i
t
d
= [R
N1
C
a
] + [(R
N1
+ R
N2
)C
b
] +
[(R
N1
+ R
N2
+ R
N3
)(C
c
+ C
p+load
)]
t
d
= [R
N1
(C
a
+C
b
+C
c
+C
p+load
)] +
[R
N2
(C
b
+C
c
+C
p+load
)] +
[R
N3
(C
c
+ C
p+load
)]

48. Progressive Sizing
• When parasitic capacitance
is significant (e.g., when fan-
in is large), needs to
consider distributed RC
effect
• Increasing the size of M1 has
the largest impact in terms of
delay reduction
•M
1
> M
2
> M
3
> …> M
N
ln
3
ln
N
Out
ln
1
ln
2
M
1
M
2
M
3
M
N

49. Delay Optimization by Transistor Ordering
ln
3
ln
N
Out
ln
1
ln
2
M
1
M
2
M
3
M
N
Critical signal next to supply
Critical path
ln
3
ln
N
Out
ln
1
ln
2
M
1
M
2
M
3
M
N
Critical signal next to output
Critical path