Computer Architecture and Organization ppt

CAO PPt

1. Computer Architecture &
Organization
20A04504a

2. •ADigitalcomputercanbeconsideredasadigital
systemthatperformsvariouscomputationaltasks.
•Thefirstelectronicdigitalcomputerwasdevelopedin
thelate1940sandwasusedprimarilyfornumerical
computations.
•Byconvention,thedigitalcomputersusethebinary
numbersystem,whichhastwodigits:0and1.A
binarydigitiscalledabit.
•Acomputersystemissubdividedintotwofunctional
entities:HardwareandSoftware.

3. Digital computer
•Thehardwareconsistsofalltheelectroniccomponentsand
electromechanicaldevicesthatcomprisethephysicalentityofthedevice.
•Thesoftwareofthecomputerconsistsoftheinstructionsanddatathatthe
computermanipulatestoperformvariousdata-processingtasks.

4. Digital computer
•Input unit
Inputunitsareusedbythecomputertoreadthedata.Themost
commonlyusedinputdevicesarekeyboards,mouse,joysticks,trackballs,
microphones,etc.
However,themostwell-knowninputdeviceisakeyboard.Whenevera
keyispressed,thecorrespondingletterordigitisautomaticallytranslatedintoits
correspondingbinarycodeandtransmittedoveracabletoeitherthememoryor
theprocessor.
•Central processing unit
CentralprocessingunitcommonlyknownasCPUcanbereferredasan
electroniccircuitrywithinacomputerthatcarriesouttheinstructionsgivenbya
computerprogrambyperformingthebasicarithmetic,logical,controland
input/output(I/O)operationsspecifiedbytheinstructions.

5. Digital computer
Memory unit
•TheMemoryunitcanbereferredtoasthestorageareainwhichprograms
arekeptwhicharerunning,andthatcontainsdataneededbytherunning
programs.
•TheMemoryunitcanbecategorizedintwowaysnamely,primarymemory
andsecondarymemory.
•Itenablesaprocessortoaccessrunningexecutionapplicationsandservices
thataretemporarilystoredinaspecificmemorylocation.
•Primarystorageisthefastestmemorythatoperatesatelectronicspeeds.
Primarymemorycontainsalargenumberofsemiconductorstoragecells,
capableofstoringabitofinformation.Thewordlengthofacomputeris
between16-64bits.
•Cachememoryisalsoakindofmemorywhichisusedtofetchthedatavery
soon.Theyarehighlycoupledwiththeprocessor.
•ThemostcommonexamplesofprimarymemoryareRAMandROM.
•Secondarymemoryisusedwhenalargeamountofdataandprogramshave
tobestoredforalong-termbasis.
•Themostcommonexamplesofsecondarymemoryaremagneticdisks,
magnetictapes,andopticaldisks.

6. Arithmetic&logicalunit
•Mostofallthearithmeticandlogicaloperationsofacomputerareexecutedinthe
ALU(ArithmeticandLogicalUnit)oftheprocessor.Itperformsarithmeticoperations
likeaddition,subtraction,multiplication,divisionandalsothelogicaloperationslike
AND,OR,NOToperations.
Controlunit
•Thecontrolunitisacomponentofacomputer'scentralprocessingunitthat
coordinatestheoperationoftheprocessor.Ittellsthecomputer'smemory,
arithmetic/logicunitandinputandoutputdeviceshowtorespondtoaprogram's
instructions.
•Thecontrolunitisalsoknownasthenervecenterofacomputersystem.
OutputUnit
•Theprimaryfunctionoftheoutputunitistosendtheprocessedresultstotheuser.
Outputdevicesdisplayinformationinawaythattheusercanunderstand.
•Outputdevicesarepiecesofequipmentthatareusedtogenerateinformationorany
otherresponseprocessedbythecomputer.Thesedevicesdisplayinformationthathas
beenheldorgeneratedwithinacomputer.
•Themostcommonexampleofanoutputdeviceisamonitor.

7. CAO?
•Ingeneralterms,thearchitectureofacomputer
systemcanbeconsideredasacatalogueoftoolsor
attributesthatarevisibletotheusersuchas
instructionsets,numberofbitsusedfordata,
addressingtechniques,etc.
•Whereas,Organizationofacomputersystemdefines
thewaysystemisstructuredsothatallthose
cataloguedtoolscanbeused.Thesignificant
componentsofComputerorganizationareALU,
CPU,memoryandmemoryorganization.

8. Computer Design and Architecture
ComputerArchitecture ComputerOrganization
CAisconcernedwiththeway
hardwarecomponentsareconnected
togethertoformacomputersystem.
COisconcernedwiththestructureand
behaviorofacomputersystemasseen
bytheuser.
Itactsastheinterfacebetween
hardwareandsoftware.
Itdealswiththecomponentsofa
connectioninasystem.
ComputerArchitecturehelpsusto
understandthefunctionalitiesofa
system.
ComputerOrganizationtellsushow
exactlyalltheunitsinthesystemare
arrangedandinterconnected.
Aprogrammercanviewarchitecture
intermsofinstructions,addressing
modesandregisters.
WhereasOrganizationexpressesthe
realizationofarchitecture.
Whiledesigningacomputersystem
architectureisconsideredfirst.
Anorganizationisdoneonthebasisof
architecture.

9. ComputerArchitecture ComputerOrganization
ComputerArchitecturedealswithhigh-
leveldesignissues.
ComputerOrganizationdealswithlow-
leveldesignissues.
ArchitectureinvolvesLogic(Instruction
sets,Addressingmodes,Datatypes,Cache
optimization)
Organizationinvolves Physical
Components(Circuitdesign,Adders,
Signals,Peripherals)

10. Register Transfer Language
•Thesymbolicnotationusedtodescribethemicro
operationtransfersamongregistersiscalleda
registertransferlanguage.
•Thesedigitalmodulesareinterconnectedwithsome
commondataandcontrolpathstoformacomplete
digitalsystem.
•Moreover,digitalmodulesarebestdefinedbythe
registersandtheoperationsthatareperformedon
thedatastoredinthem.
•Theoperationsperformedonthedatastoredin
registersarecalledMicro-operations.

11. Register transfer
•Digital systems are composed of modules that
are constructed from digital components, such
as registers, decoders, arithmetic elements,
and control logic.
•Replacement Operator :
In the statement, R2 <-R1,<-acts as a
replacement operator. This statement defines
the transfer of content of register R1 into
register R2.
•

12. •A micro operation is an elementary operation
performed on the information stored in one or
more registers. Examples are shift, count,
clear, and load.
•Some of the digital components are registers
that implement micro operations.

13. REGISTER TRANSFER:
•Designate computer registers by capital letters
to denote its function.
•The register that holds an address for the
memory unit is called MAR.
•The program counter register is called PC.
•IR is the instruction register and R1 is a
processor register.
•The individual flip-flops in an n-bit register are
numbered in sequence from 0 to n-1.

16. Tri-state buses

25. Instruction Codes
•Group of bits that instruct the computer to perform specific operation.
•Instruction code is usually divided into two parts: opcodeand address
OPERATION CODE
Group of bits that define the operation
No. of bits required for opcodedepends on no. of operations available in
computer
n bit opcode>= 2n (or less) operations
ADDRESS
Specifies the location of operands (registers or memory words)
Memory words are specified by their address
Registers are specified by their k-bit binary code
k-bit address >= 2k registers

26. STORED PROGRAM ORGANIZATION

28. COMPUTER REGISTERS

29. Register in Computer

30. Computer Instructions

32. Instruction Cycle

33. Flow Chart

34. Timing & Control
Hardwired control Micro programmed control
The control logic is implemented with
gates, flip-flops, decoders, and other
digital circuits
Thecontrolinformationisstoredina
controlmemory.Thecontrolmemory
isprogrammedtoinitiatethe
requiredsequenceofmicro-
operations.
The advantage that it can be
optimized to produce a fast mode of
operation.
Comparedwithoperationisslow.the
hardwiredcontrol
Requires changes in the wiring among
the various components if the design
has to be modified or changed.
Required changes or modifications
can be done by updating the micro-
program in control memory.
The timing for all registers in the basic computer is controlled by a master
clock generator.
The clock pulses do not change the state of a register unless the register is
enabled by a control signal.

35. Timing & Control

36. Timing Diagram

39. Micro programmed control organization

41. MICROPROGRAM EXAMPLE

45. DESIGN OF CONTROL UNIT

48. GENERAL REGISTER ORGANIZATION

50. STACK ORGANIZATION
•Astackorlast-infirst-out(LIFO)isusefulfeaturethat
isincludedintheCPUofmostcomputers
•Astackisastoragedevicethatstoresinformationin
suchamannerthattheitemstoredlastisthefirst
itemretrieved.
•Theregisterthatholdstheaddressforthestackis
calledastackpointer(SP).Italwayspointsatthetop
iteminthestack.
•Thetwooperationsthatareperformedonstackare
theinsertionanddeletion.

51. Register STACK Memory STACK

53. TWO ADDRESS INSTRUCTIONS
THREE ADDRESS INSTRUCTIONS
Instruction Format
Three-address instruction formats can use each address field to specify
either a processor register or a memory operand.

54. ONE ADDRESS INSTRUCTIONS
•One-address instructions use an implied accumulator (AC) register for all data
manipulation
•For multiplication and division there is a need for a second register.

55. •A stack-organized computer does not use an address field for the instructions ADD
and MUL
•The PUSH and POP instructions, however, need an address field to specify the
operand that communicates with the stack.
ZERO ADDRESS INSTRUCTIONS

56. RISC INSTRUCTIONS
•RISC processor is use only load and store instructions for communicating between
memory and CPU.
•All other instructions are executed within the registers of CPU without referring to
memory.
•LOAD and STORE instructions that have one memory and one register address, and
computational type instructions that have three addresses with all three specifying
processor registers.

57. ADDRESSING MODES
AddressingModes Operation
IMPLIED MODE Doesn’t require anyaddress fields
IMMEDIATE MODE Operand is specified in the instruction itself
REGISTER MODE Register is selected from a register field in the instruction.
REGISTER INDIRECT MODEThe instruction specifies a register in CPU whose contents give
the address of the operand in memory.
AUTO-INCREMENT OR
AUTO-DECREMENT MODE
The instructionspecifies both increment and decrement
functions in the registers
DIRECT ADDRESS MODE The effective address is equal to the address part of the
instruction.
INDIRECT ADDRESS MODEThe effective address is stored in memory.
RELATIVE ADDRESS MODEContent of the program counter is added to the address part
of the next instruction in order to obtain the effective
address.
INDEXED ADDRESSING
MODE
content of an index register is added to the address part of
the instruction to obtain the effective address

59. Operations

60. Data Transfer and Manipulation
•Most computer instructions can be classified into three
categories:
1.Data transfer instructions
2. Data manipulation instructions
3. Program control instructions
•Data Transfer Instructions
–Data transfer instructions move data from one place in the
computer to another without changing the data content.
–The most common transfers are between memory and
processor registers, between processor registers and input
or output, and between the processor registers themselves.

61. Arithmetic Operations
Increment
Decrement
Add
Subtract
Multiply
Divide
Add with carry
Subtract with borrow
Negate (2's
complement)
INC
DEC
ADD
SUB
MUL
DIY
ADDC
SUBB
NEG
Logical shift right
Logical shift left
Arithmetic shift right
Arithmetic shift left
Rotate right
Rotate left
Rotate right through carry
Rotate left through carry
SHR
SHL
SHRA
SHLA
ROR
ROL
RORC
ROLC
Logical and Bit Manipulation Instructions
Clear
Complement
AND
OR
Exclusive-OR
Clear carry
Set carry
Complement carry
Enable interrupt
Disable interrupt
CLR
COM
AND
OR
XOR
CLRC
SETC
COMC
El
Dl

62. PROGRAM CONTROL
Programcontrolinstructionsspecifyconditionsforalteringthecontentofthe
programcounter.
Thechangeinvalueoftheprogramcounterasaresultoftheexecutionofaprogram
controlinstructioncausesabreakinthesequenceofinstructionexecution
Thisinstructionprovidescontrolovertheflowofprogramexecutionandacapability
forbranchingtodifferentprogramsegments

63. STATUS BIT CONDITIONS

65. Data Types
•Dataandinstructionscannotbeenteredand
processeddirectlyintothecomputersusing
humanlanguage
•Anytypeofdatamustfirstbeconvertedinto
machine-readableformi.e.binaryform.
•Binaryinformationindigitalcomputersis
storedinmemoryorprocessorregisters.
•Registerscontaineitherdataorcontrol
information.

66. Addition and Subtraction

69. MULTIPLICATION ALGORITHMS
•The multiplication of two numbers in signed
magnitude representation is carried out by
successive shift and adds

75. Array Multiplier

78. FLOATING-POINT ARITHMETIC
OPERATIONS

79. Afloating-pointnumberincomputerregisterscontainsoftwo
parts:amantissa‘m’andanexponent‘e’.Thetwoparts
representanumberobtainedfrommultiplying‘m’timesaradix
‘r’raisedtothevalueofe;
m x re
The algorithm can be divided into four
consecutive parts:
1. Check for zeros.
2. Align the mantissas.
3. Add or subtract the mantissas.
4. Normalize the result.

81. Multiplication
•Themultiplicationoftwofloating-pointnumbersrequiresthat
wemultiplythemantissasandaddtheexponents.
•Nocomparisonofexponentsoralignmentofmantissasis
necessary
•multiplicationissubdividedintofourparts
1. Check for zeros.
2. Add the exponents.
3. Multiply the mantissas.
4. Normalize the product.

83. Division
•Floating-pointdivisionrequiresthattheexponentsbe
subtractedandthemantissasdivided.
•divisionalgorithmissubdividedinto
–1. Check for zeros.
–2. Initialize registers and evaluate the sign.
–3. Align the dividend.
–4. Subtract the exponents.
–5. Divide the mantissas.

85. Decimal Arithmetic Unit
•Computerscapableofperformingdecimalarithmetic
muststorethedecimaldatainbinarycodedform.
•Thedecimalnumbersarethenappliedtoadecimal
arithmeticunitcapableofexecutingdecimal
arithmeticmicrooperations
•Adecimalarithmeticunitisadigitalfunctionthat
performsdecimalmicrooperations.Itcanaddor
subtractdecimalnumbers,

88. Binary subtraction

91. Multiplication

93. I/0 Bus and Interface Modules

95. ASYNCHRONOUS DATA TRANSFER
•Iftheregistersintheinterfaceshareacommonclockwiththe
CPUregisters,thetransferbetweenthetwounitsissaidtobe
synchronous.
•Inmostcases,theinternaltimingineachunitisindependent
fromtheotherinthateachusesitsownprivateclockfor
internalregisters.Itiscalledasynchronous.
•Asynchronousdatatransferbetweentwoindependentunits
requiresthatcontrolsignalsbetransmittedbetweenthe
communicatingunits.
•There are two methods are used to supply control signals.
–Strobe control
–Handshaking

96. •Strobe Control:

97. Handshaking

99. Asynchronous Communication Interface

101. MODES OF TRANSFER
•Data transfer to and from peripherals may be
handled in one of three possible modes:
•Programmed I/O
•Interrupt-initiated I/O
•Direct memory access (DMA)

103. Interrupt initiated I/O:

104. Daisy Chain

105. Parallel Priority Interrupt

106. DMA Controller
•DMAControllerisahardwaredevicethatallowsI/O
devicestodirectlyaccessmemorywithless
participationoftheprocessor

107. TheDMA controller registershave three
registers as follows.
–Addressregister–Itcontainstheaddressto
specifythedesiredlocationinmemory.
–Wordcountregister–Itcontainsthenumberof
wordstobetransferred.
–Controlregister–Itspecifiesthetransfermode.

108. DMA Controller

109. RAM: Volatile
ROM: Non-Volatile

110. RAM ROM
RAM is used to designate read/write to
distinguish it from a ROM.
ROM is used to designate read operation
only.
RAM is used for storing the bulk of the
programs and data that are subject to
change
ROM is used for storing programs that are
permanently resided in the computer and
that don’t change.
RAM is volatile; its contents are destroyed
when power is turned off.
ROM is nonvolatile; its contents are not
destroyed when power is turned off.
It has a bidirectional data bus. It has a unidirectional data bus

112. Auxiliary Memory
•An Auxiliary memory is known as the lowest-cost,
highest-capacity and slowest-access storage in a
computer system.
•Programs and data are kept for long-term storage
•Magnetic Disks
–A magnetic disk is a type of memory constructed using a
circular plate of metal or plastic coated with magnetized
materials.

113. The memory bits are stored in the magnetized surface in spots
along the concentric circles called tracks.
The concentric circles (tracks) are commonly divided into
sections called sectors.

114. Associative Memory
•Anassociativememorycanbeconsideredasamemoryunit
whosestoreddatacanbeidentifiedforaccessbythecontent
ofthedataitselfratherthanbyanaddressormemory
location.
•AssociativememoryisoftenreferredtoasContent
AddressableMemory(CAM)

116. CACHE MEMORY
•Locality of Reference: The references to memory at any given
time interval tends to be confined within a localized area.
•When a program loop is executed, the CPU repeatedly refers to
the set of instructions in memory that constitute the loop.
•Three types of mapping procedures are :
1. Associative mapping
2. Direct mapping
3. Set-associative mapping

117. Associative mapping
•Thefastestandmostflexiblecacheorganizationusesanassociative
memory.
•Theassociativememorystoresbothaddressandcontent(data)ofthe
memoryword.
•ACPUaddressof15bitsisplacedintheargumentregisterandthe
associativememoryissearchedformatchingaddress.Iftheaddressis
found,thecorresponding12-bitdataisreadandsenttotheCPU

118. Direct mapping
•The CPU address of 15 bits is divided into two fields. The 9 least significant
bits constitute the index field and the remaining 6 bits from the tag field.

119. Set associative mapping
•Theset‒Associativemappingisanimprovementoverthedirectmapping
organizationinthateachwordofcachecanstoretwoormorewordsof
memoryunderthesameindexaddress.
•Each data word is stored together with its tag and the number of tag‒data
items in one word of cache is said to form set.

120. RISC Processor
•RISCstandsforReducedInstructionSetComputerProcessor,
microprocessorarchitecturewithasimplecollectionandhighly
customizedsetofinstructions.
•Itisbuilttominimizetheinstructionexecutiontimeby
optimizingandlimitingthenumberofinstructions
•Itmeanseachinstructioncyclerequiresonlyoneclockcycle,and
eachcyclecontainsthreeparameters:fetch,decodeand
execute.
•AdvantagesofRISCProcessor
–The RISC processor's performance is better due to the simple and limited
number of the instruction set.
–RISC processor is simpler than a CISC processor because of its simple and
quick design, and it can complete its work in one clock cycle.

121. Characteristics of RISC Processor
•Onecycleexecutiontime:Forexecutingeachinstructioninacomputer,the
RISCprocessorsrequireoneCPI(Clockpercycle).AndeachCPIincludesthe
fetch,decodeandexecutemethodappliedincomputerinstruction.
•Pipeliningtechnique:ThepipeliningtechniqueisusedintheRISC
processorstoexecutemultiplepartsorstagesofinstructionstoperform
moreefficiently.
•Alargenumberofregisters:RISCprocessorsareoptimizedwithmultiple
registersthatcanbeusedtostoreinstructionandquicklyrespondtothe
computerandminimizeinteractionwithcomputermemory.
•supportsasimpleaddressingmodeandfixedlengthofinstructionfor
executingthepipeline.
•ItusesLOADandSTOREinstructiontoaccessthememorylocation.
•Simpleandlimitedinstructionreducestheexecutiontimeofaprocessina
RISC.

122. CISC Processor
•TheCISCStandsforComplexInstructionSetComputer,
developedbytheIntel.Ithasalargecollectionofcomplex
instructionsthatrangefromsimpletoverycomplexand
specializedintheassemblylanguagelevel.
•CISCapproachesreducingthenumberofinstructiononeach
programandignoringthenumberofcyclesperinstruction.
•CharacteristicsofCISCProcessor
–1. The length of the code is shorts, so it requires very little RAM.
–2. CISC or complex instructions may take longer than a single clock cycle
to execute the code.
–3. Less instruction is needed to write an application.
–4. It provides easier programming in assembly language.
–5. Support for complex data structure and easy compilation of high-level
languages.
–6. It is composed of fewer registers and more addressing nodes, typically
5 to 20.

123. RISC CISC
RISC is a Reduced Instruction Set
Computer
CISC is a Complex Instruction Set
Computer
There are few addressing modes There are many addressing modes.
There are few instructions. There are many instructions
It can include simple instructions and
takes one cycle.
It can include complex instructions and
takes multiple cycles
Hardware executes the instructions. Micro-program executes the instructions
There are Fixed format instructions. There are Variable format instructions.
It can be easier to decode as instructions
have a fixed format
It can be complex to decode as
instructions have variable format
RISC is highly pipelined CISC is less pipelined

124. Overlapped Registers

125. RISC Pipeline
•ThedatatransferinstructionsinRISCarelimitedtoloadandstore
instructions.
•The instruction cycle can be divided into three sub-operations and
implemented in three segments
•I: Instruction fetch
–Fetches the instruction from program memory
•A: ALU operation
–The instruction is decoded and an ALU operation is performed.
–It performs an operation for a data manipulation instruction.
–It evaluates the effective address for a load or store instruction.
–It calculates the branch address for a program control instruction.
•E: Execute instruction
–Directs the output of the ALU to one of three destinations, depending on the decoded
instruction.
–It transfers the result of the ALU operation into a destination register in the register file.
–It transfers the effective address to a data memory for loading or storing.
–It transfers the branch address to the program counter.

126. •Delayed Load
–Consider the operation of the following four
instructions:
–LOAD: R1 M[address 1] , LOAD: R2 M[address 2]
–ADD: R3 R1 +R2 , STORE: M[address 3] R3

127. Delayed Branch
•ThemethodusedinmostRISCprocessorsistorelyonthecompilerto
redefinethebranchessothattheytakeeffectatthepropertimeinthe
pipeline.Thismethodisreferredtoasdelayedbranch.
•Thecompilerisdesignedtoanalyzetheinstructionsbeforeandafterthe
branchandrearrangetheprogramsequencebyinsertinguseful
instructionsinthedelaysteps.

128. PARALLEL PROCESSING
•Aparallelprocessingsystemis
abletoperformconcurrentdata
processingtoachievefaster
executiontime
•Thesystemmayhavetwoormore
ALUsandbeabletoexecutetwo
ormoreinstructionsatthesame
time
•Goal is to increase the throughput
–the amount of processing that
can be accomplished during a
given interval of time

129. INTERPROCESSOR ARBITRATION

131. Interconnection Structures
•1. Time-shared common bus
•2. Multiport memory
•3. Crossbar switch
•4. Multistage switching network
•5. Hypercube system

132. Multiport Memory

133. Cross bar Switch

134. Multistage Switching Network