Computer architecture chapter 5 bca.pptx

Important for exam

1. BASIC COMPUTER ORGANIZATION AND DESIGN Computer Architecture Asst.Prof.Niveditha P (CICMS)

2. Instruction codes A computer instruction is a binary code that determines the micro-operations in a sequence for a computer. They are saved in the memory along with the information. Each computer has its specific group of instructions . They can be categorized into two elements as Operation codes (Opcodes) and Address. The   Op code  of an instruction is a group of bits that define operations such as addition, subtraction, shift, complement, etc . The Operand specifies the address of the data. Op Code Address of Operand 11 12 15

3. Stored program organization The first part of an instruction code format is the Opcode and the second is the address of the Operand. It is a total of 16 bit register. The first 12 bits is for the address of Operand. The next 4 bit is for the Opcode which is split as 3 + 1. 3 bit for code and 1 bit for address mode. If address mode is 0 – Direct Addressing If address mode is 1 – Indirect Addressing i Op Code Address of Operand 11 12 15 14

4. Direct Address & Indirect Address

5. Computer Registers Registers are a type of computer memory used to quickly accept, store, and transfer data and instructions that are being used immediately by the CPU. The registers used by the CPU are often termed as Processor registers. A processor register may hold an instruction, a storage address, or any data (such as bit sequence or individual characters). The computer needs processor registers for manipulating data and a register for holding a memory address. The register holding the memory location is used to calculate the address of the next instruction after the execution of the current instruction is completed.

6. Following is the list of some of the most common registers used in a basic computer: Register Symbol Number of bits Function Data register DR 16 Holds memory operand Address register AR 12 Holds address for the memory Accumulator AC 16 Processor register Instruction register IR 16 Holds instruction code Program counter PC 12 Holds address of the instruction Temporary register TR 16 Holds temporary data Input register INPR 8 Carries input character Output register OUTR 8 Carries output character

7. Common Bus System 6 registers (AR, PC, DR, AC, IR and TR) and memory unit are connected to common bus. The DR (Data Register) is also connected with the ADDER and Logic Unit to perform operations on data through data Bus. INPTR (Input register) is not connected with the common bus. it receives data directly for Input device and sends it to Adder and Logic unit (part of ALU) for operations (+, -,*, /) and then pass it to Accumulator register. The adder and logic unit also contains a carry bit called (E) in case of addition . OUTR (Output Register) does not send data to a common bus or any other register because it sends directly to the output device but it receives data from the common bus . Important Every register in the system is connected with Clock Signals. Clock Signal controls LD, INR (increment), CLR (Clear register) commands by the control unit. Memory read (R) and writes (W) operation also controlled by Control Unit .

8. Working of Common Bus System Step I:  Any register can send its data to a common bus by activating its selected lines (S2, S1, S0). Step II:  If any register wants to receive data then its LD command will activate by setting the LD command value to 1. And LD command of all others registers set to zero. Step III:  Main process starts with the program counter. Program counter fetches the address of memory which has to execute. And then pass this address to common bus. AR receive the address from common bus by activating its LD bits. Then AR sends the address to memory directly because AR is directly connected with common bus. Memory read the address and sends Data of that address to DR through common Bus. Step IV:  Memory fetched data will be in DATA Register and then pass to Accumulator register by Data BUS because DR is directly connected with AC by Data Bus. Copy of this data is transfer to IR because when data pass to the accumulator register then Data Register will flush-out. So that the next incoming data in the next cycle can store. If the Accumulator register wants to store, (received data form DR) temporary in somewhere then it passes it to Temporary register (TR). If we want to retrieve the data from TR then its data is first loaded in DR and then it passes to AC. Note : Activation/Deactivation of LD, INR or CLR of any register is done through a circuit called control unit. Note: Other name of DR (data register) are MBR or MDR.

9. COMPUTER INSTRUCTIONS The computer has three instruction code formats. Each format has 16 bits. Memory Reference Instructions : it uses 12 bits to specify address, 3 bit for the opcode, 1 bit for indirect or direct address. 2. Register Reference Instructions : 0111 – specifies it is a register instruction. 12 bits are used to specify the operation to be performed/executed. 3. Input – Output Instructions : are recognised by 1111 and the remaining 12 bits specify the type of I/O Operation. i Op Code Address 11 12 15 14 1 1 1 Register Operation 11 12 15 1 1 1 1 Address of Operand 11 12 15

10. HARDWARE CONTROL UNIT/ CONTROL UNIT OF BASIC COMPUTER

11. There are two decoders. 1 – A Sequence Counter. 2 – number of C ontrol Logic Gates. IR – Instruction Register. It is divided into 3 parts. 1- I bit (1 bit) 2- operand code (3 bits) 3- bits 0 through 11 (12 bits) The operation code in the bits 12, 13, 14 are decoded with a 3x8 decoder. We will get 8 outputs of the decoder. D0,D1,D2,D3,D4,D5,D6,D7 The ‘ i ’ bit is transferred to a flip-flop. Bits 0 to 11 are applied to the control logic gates. The 4 bit sequence counter (SC) can count in binary form 0 through 15. The output of the counter are decoded into 16 timing Signals. T0,T1,T2………..T15

12. Instruction Cycle

13. A program residing in the memory unit of a computer consists of a sequence of instructions. These instructions are executed by the processor by going through a cycle for each instruction. In a basic computer, each instruction cycle consists of the following phases: Fetch instruction from memory. Decode the instruction. Read the effective address from memory. Execute the instruction.

14. The circuits used in the CPU during the cycle are: Program Counter (PC)  - an incrementing counter that keeps track of the memory address of which instruction is to be executed next. Memory Address Register (MAR)  - holds the address in memory of the next instruction to be executed. Memory Data Register (MDR)  - a two-way register that holds data fetched from memory (and ready for the CPU to process) or data waiting to be stored in memory. Instruction register (IR)  - a temporary holding ground for the instruction that has just been fetched from memory. Control Unit (CU)  - decodes the program instruction in the CIR, selecting machine resources such as a data source register and a particular arithmetic operation, and coordinates activation of those resources. Arithmetic logic unit (ALU)  - performs mathematical and logical operations. Each computer's CPU can have different cycles based on different instruction sets, but will be similar to the following cycle :

15. 1. Fetch the instruction The next instruction is fetched from the memory address that is currently stored in the Program Counter (PC), and stored in the Instruction register (IR). At the end of the fetch operation, the PC. points to the next instruction that will be read at the next cycle. Clock Pulse: T0-T1 2. Decode the instruction The decoder interprets the instruction. During this cycle the instruction inside the IR (instruction register) gets decoded. Clock Pulse: T2 3. Read the effective address In case of a memory instruction (direct or indirect) the execution phase will be in the next clock pulse. If the instruction has an indirect address, the effective address is read from main memory, and any required data is fetched from main memory to be processed and then placed into data registers (Clock Pulse: T3). If the instruction is direct, nothing is done at this clock pulse. If this is an I/O instruction or a Register instruction, the operation is performed (executed) at clock Pulse: T3. Clock Pulse: T3 4. Execute the instruction The CU passes the decoded information as a sequence of control signals to the relevant function units of the CPU to perform the actions required by the instruction such as reading values from registers , passing them to the ALU to perform mathematical or logic functions on them, and writing the result back to a register. If the ALU is involved, it sends a condition signal back to the CU. Clock Pulse: T3-T6 (Up to T6) The result generated by the operation is stored in the main memory, or sent to an output device. Based on the condition of any feedback from the ALU, Program Counter may be updated to a different address from which the next instruction will be fetched. The cycle is then repeated.

16. Instructions : 1.Load:  This miniature activity loads information from memory into a register. 2.Store:  This miniature activity stores information from a register into memory. 3.Add : This miniature activity adds two qualities and stores the outcome in a register. 4.Subtract:  This miniature activity deducts two qualities and stores the outcome in a register . 5.And:  This miniature activity plays out a legitimate AND procedure on two qualities and stores the outcome in a register. 6.Or:  This miniature activity plays out a legitimate OR procedure on two qualities and stores the outcome in a register. 7.Not:  This miniature activity plays out a legitimate NOT procedure on a worth and stores the outcome in a register. 8.Shift:  This miniature activity moves the pieces of a worth to the left or right. 9.Rotate:  This miniature activity pivots the pieces of a worth to the left or right.

17. Input-Output Configuration: The input-output terminals send and receive information. The amount of information transferred will always have eight bits of an alphanumeric code. The information generated through the keyboard is shifted into an input register 'INPR'. The information for the printer is stored in the output register 'OUTR'. Registers INPR and OUTR communicate with a communication interface serially and with the AC in parallel. The transmitter interface receives information from the keyboard and transmits it to INPR. The receiver interface receives information from OUTR and sends it to the printer serially .