Computer Organisation and Architecture Unit I .pdf

Computer Organisation and Architecture

1. Computer Organization and
Architecture
COURSE CODE
CS229(SY-CE/IT)

2. WhytoStudyComputerOrganization&Architecturecourse?
Studentswilluseknowledgeofiteverydayandfortherestoflifeaswell.
AsCOAisperhapsthemostfundamentalsubjectincomputerscience.
Knowingwhat'sinsidecomputerandhowitworkswillhelpstudentstodesign
anddevelopnewsystem.
Itwillhelpstudentstoimplementapplicationsinbetter,faster,cheaper,more
efficientandeasierway.
COAfocusesondesignofvariouscomponentsnecessarytoprocess
informationdigitallye.g.memory,ALU,CU,IOdevicesetc.

3. ThestudyofCOAfocusesontheinterfacebetweenhardwareandsoftware.
COAcourseisimportantintheGATEexaminationpointofview.(5-11
marks/100).
BecauseofthesereasonsCOA/COcourseisincorporatedineveryuniversity
syllabusasacompulsory&coresubject.

4. Comparison between old COA and new COA syllabus
Lab component is newly introduced with this course.
Old Digital Electronics and Microprocessor course and one unit of ACA from
old TY COA are removed.
This course is combination of three courses that is DEM, CO & ACA/HPC
Nearly 35% syllabus of old COA is changed

5. TEACHING SCHEME : EVALUATION SCHEME :
LECTURE PRACTICAL
THEORY
PRACTICAL
PRESENTATION/
DEMONSTRATION
TOTAL
MSE ESE IA
3 2 35 35 30 50 - 150
PRE-REQUISITE:
1.EX102-Electrical & Electronics Engineering

6. COURSE OBJECTIVES:
CS.CEO.1:TounderstandtheArchitectureof80386.
CS.CEO.2:TogetfamiliarwithAssemblylanguageprogramming.
CS.CEO.3:TounderstandtheInputOutputorganizationand
controlunitofcomputersystem
CS.CEO.4:Togetfamiliarwiththememoryorganizationofthe
computersystem
CS.CEO.5:Tolearnworkingofarithmeticunitofthecomputer
system.
CS.CEO.6:Todifferentiatevariousorganizationsforhigh
performancecomputing

7. COURSEOUTCOMES:
Studentssuccessfullycompletingthecoursewillbeableto
CS.CO.1:Explainthearchitectureofthe80386processor.
CSCO.2:Designandwriteassemblylanguageprogramsfor
differenttasks.
3CS.CO.3:IllustrateIOorganizationsandcontrolunit.
CS.CO.4:Analyzevariousmemoryorganizationtechniquessuchas
Segmentation,Paginginthecomputersystem.
CS.CO.5:Illustratearithmeticoperations.
CS.CO.6:Comparevariousparallelprocessingarchitecturesand
environments

8. THEORY:
Architecture of 80386 Processor 6 Hours
App/System/Casestudy:
Pentiumprocessors
Contents:
80386Architecture,Featuresof80386,Registers,GlobalDescriptor
Table,LocalDescriptorTable,InterruptDescriptorTable,DataTypes,
80386addressingmodes,CISC,RISC.Intelcorei9processor
Selfstudy:Pentiumprocessorarchitecture
FurtherReading:Intelcorei9processorarchitecture

9. Unit IIInput/output organization and Control unit 6 Hours
App/System/Casestudy:
Input/outputDevices
Contents:
Input-OutputOrganization:AccessingI/Odevices,Interrupts,direct
memoryaccess.Buses.StandardIOinterfaces,PCI,SCSI.
ControlUnit-Basicconcepts,Microprogrammed control,Hardwired
control,Pipelinecontrol.
SelfStudy:InterfaceCircuits.
Furtherreading:USB.

10. Unit IIIThe Memory System 5 Hours
App/System/Casestudy:
Memoryhierarchy
Contents:
Basicconcepts,semiconductorRAMmemories,read-only
memories,speed,sizeandcost,cachememories,DRAM,
SRAM,RAID,virtualmemory.SSD.
SelfStudy:Secondarystorage
Furtherreading:Flashmemory

11. Unit IVSegmentation,Pagingand Multitasking 9 Hours
App/System/Casestudy:
MMUini7Processor
Contents:
Segmentation–Introduction,supportregisters,relatedinstructions,descriptors,
memorymanagement throughsegmentation,logicaltolinearaddress
translations,protectionbysegmentation,privilege-level,protectionrelated
instructions,inter-privilegelevel,transfercontrol,Paging-supportregisters,related
datastructures,lineartophysicaladdresstranslation,TLB,pagelevel
protection.
Multitasking-supportregisters,relateddatastructures,Taskswitching,Nested
task.
SelfStudy:Protectedmodeinstructions
Furtherreading:SegmentationandPaginginPentiumProcessor

12. Unit VArithmetic Operations 6 Hours
App/System/Casestudy:
Binaryrepresentationofprogram
Contents:
DesignofFastAdders,Additionofpositivenumbers,Additionand
SubtractionofSignedNumbers,MultiplicationofPositiveNumbers,
SignedOperandMultiplication,FastMultiplication,Floating-point
NumbersandOperations.
SelfStudy:Integerdivision
Furtherreading:Floatingpointprocessorarchitecture.

13. Unit VIPipelining 6 Hours
App/System/Casestudy:
UltraSPARCIIArchitecture
Contents:
Flynn'sClassification,BasicConcepts,DataHazards,Instruction
hazards,influenceoninstructionsets,datapathandcontrol
considerations,Superscalar,Performanceconsiderations,SIMD
GPUarchitecture.
SelfStudy:SMPArchitecture
Furtherreading:CC-NUMAArchitecture.

14. TEXT BOOK:
1.DouglasV.Hall,“MicroprocessorsandInterfacingProgrammingandHardware”,
8086.80286.80386.80486,SecondEdition,TataMcGrawHil
2.Intel80386Programmer'sReferenceManual1986,IntelCorporation,Orderno.:
231630-011,December1995.
3.BarryB.Brey,“TheIntelMicroprocessors:8086/8088,80186/80188,80286,80386,
80486,Pentium, PentiumproProcessor,PentiumII,PentiumIII,Pentium4,and
Core2...-Architecture,Programming,andInterfacing”.
4.W.Stallings,“ComputerOrganizationandArchitecture:Designingfor
performance”,PearsonEducation/PrenticeHallofIndia,2003,ISBN978-93-325-
1870-4,7thEdition.
5.ZakyS,Hamacher,“ComputerOrganization”,5thEdition,McGraw-Hill
Publications,2001,ISBN-978-1-25-900537-5,5thEdition.

15. REFERENCES:
1.M Morris Mano “Digital Logic and Computer Design” 1/e
Pearson, June 2016.
2.Kauffmann, “Computer System Architecture” by M. Mano, 2001,
Prentice-Hall ISBN 72157661505664197
3.John P Hays, “Computer Architecture and Organization”,
McGraw-Hill Publication, 1998, ISBN:9781259028564, 3rd Edition.

16. Type Examination Syllabus Marks Total Marks
MSE
Unit No. 1,2
& 3
35
ESE
Unit No. 1 to
6
35
Internal
Assessment
Unit No. 1 to
6
60
Continuous
Assessment
Practical
List
80 (10
marks per
practical
title)
End Sem
Assessment
Practical
List
40
Written exam /Online
examination
Activity, Assignments,
Quiz, Presentations etc.
Written exam /Online
examination
100
EXAMINATION SCHEME
Practical Exam/
Demonstration/ Report/
Review
Writing
Practical
performance
35
30
15
35
Mode of Assessment
Weightage in
Final Score
35
50
Practical
(CS229L)
Theory
(CS229)

17. Sr. No.
Course
Objective
Type of
Assessment
LMS/
Tools
Used
Tentative
Date of
Conduction
Activity 1
CO1 &
CO2
Online Collpoll
Activity 2 CO3 Online Collpoll
Activity 3 CO4 Online Collpoll
Activity 4 CO4 Online Collpoll
Activity 5 CO5 Online Collpoll
Activity 6 CO6 Online Collpoll
10/2/2021
24/3/2021
12/4/2021
28/4/2021
13/1/2021
1/2/2021
10
10
10
10
INTERNAL ASSESSMENT DETAILS
Name
Theory Assignment & Poster
making with presentaion
Theory Assignments
Quiz
Theory Assignments
Quiz
Marks
10
10
Quiz Moodle
/
Socrative
/

18. Non graded activities
Guest lectures
Flipped classroom, Jigsaw activities
Field visit
Computer assembling and maintenance workshop

19. Historical perspective of computer system
First Generation
The period from 1940 to 1956 is roughly considered as the First Generation
of Computer.
The first generation computers were developed by using vacuum tube or
thermionic valve machine.
The input of this system was based on punched cards and paper tape;
however, the output was displayed on printouts.
The first generation computers worked on binary-coded concept (i.e.,
language of 0-1).
Examples:ENIAC, EDVAC, etc.

20. ENIAC

21. SecondGeneration
Theperiodfrom1956to1963isroughlyconsideredastheperiodofSecond
GenerationofComputers.
Thesecondgenerationcomputersweredevelopedbyusingtransistor
technology.
Incomparisontothefirstgeneration,thesizeofsecondgenerationwas
smaller.
Incomparisontocomputersofthefirstgeneration,thecomputingtimetaken
bythecomputersofthesecondgenerationwaslesser.
Examples:IBM1401,IBM7090and7094,UNIVAC1107,PDP-1.

26. Fourth generation Computer

27. FifthGeneration
Theperiod2010totilldateandbeyond,roughlyconsideredastheperiodof
fifthgenerationofcomputers.
Bythetime,thecomputergenerationwasbeingcategorizedonthebasisof
hardwareonly,butthefifthgenerationtechnologyalsoincludedsoftware.
Thecomputersofthefifthgenerationhadhighcapabilityandlargememory
capacity.
Workingwithcomputersofthisgenerationwasfastandmultipletaskscould
beperformedsimultaneously.
Someofthepopularadvancedtechnologiesofthefifthgenerationinclude
Artificialintelligence,Quantumcomputation,Nanotechnology,Parallel
processing,etc.

32. 4-Bit Microprocessors
8-Bit Microprocessors
16-Bit Microprocessors
32-Bit Microprocessors
64-Bit Microprocessors
History of Microprocessor

33. Introductıon
It had number ofemployees around 110,800 (2020) 77.87 billion U.S. dollars revenue

34. Intel 4004
Introduced in 1971.
It is the first microprocessor by Intel.
It is a 4-bit µP.
Its clock speed was 740KHz.
It had 2,300 transistors.
It could execute around 60,000 instructions per
second.

35. Introduced in 1976.
It is 8-bit µP.
It’s clock speed is 3 MHz.
Its data bus is 8-bit and address bus is 16-bit.
It had 6,500 transistors.
Could execute 7,69,230 instructions per second.
It could access 64 KB of memory.(2^16)
It had 246 instructions.
Over 100 million copies were sold.
Intel 8085

36. Intel 8086

37. Intel 80286

38. Intel 80386

39. MMXis a single instruction, multiple data (SIMD)

40. (Cores 4)
(For gaming and HD multimedia)

41. Intel Core i7

42. Computer system
A computer has the
following main units:
Input Unit
Output Unit
Memory Unit
Central Processing Unit

43. https://www.youtube.com/watch?v=FRCXF1Sak7s

46. Understanding C program Compilation Process

51. Architecture of 80386 Processor
Salient Features of 80386
First 32-bit microprocessor in the x86 family
80286 architecture expanded for 32 bit operation
32-bit Processor
32-bit ALU, 32-bit Registers, 32-bit Data Bus, 32-bit Address Bus
Uses 32-bit address for memory and 16-bit address for I/O ports
Maximum physical memory 4 Gb.
Maximum number of I/O ports 64 K.
Built-in Memory Management Unit to support Segmentation, Paging and
Virtual Memory.(e.g. Working of post office)

52. It supports 8/16/32 bit data operands (downwards compatibility)
It has 32-bit internal registers
It supports 32-bit data bus and 32-bit non-multiplexed address bus
It supports
Physical Address of 4GB
Virtual Address of 64TB (16384*4 GB)
Maximum Segment size of 4GB

53. It operates in 3 different modes
Real
Protected
Virtual 8086
MMU provides virtual memory, paging and 4 levels of
protection
Clock Frequency : 16 MHz,20MHz,25 MHz and 33MHz
It has 132/100 pin package
Pipelined architecture (Car assembly).
It can operate on 17 different data types (rich).
It support numeric 80387co-processor.

54. Two versions of 80386 are which are commonly available are:
1) 80386DX 2)80386SX
80386DX 80386SX
1)32 bit address bus 1) 24 bit address bus 16
data bus 32 bit bitdata bus
2)Packaged in 132 pin ceramic 2) 100 pin flat
3) Address 4GB of memory 3) 16 MB of Memory
4) Fetch 4 bytes at a time 4) Fetch 2 bytes at a
time

55. Development of microprocessor
Decode
Unit
Bus interface unit
Address unit
Inst. Unit
Exec. Unit
Segmentation Unit
Paging Unit
Pre fetch unit

56. 132 Pin diagram of 80386DX
(e.g. 80387)

57. W/R#:Thewrite/readoutputdistinguishesthewriteandread
cyclesfromoneanother.
•D/C#:Thisdata/controloutputpindistinguishesbetweena
datatransfercyclefromamachinecontrolcycle.
•M/IO#:Thisoutputpindifferentiatesbetweenthememory
andI/Ocycles.
•LOCK#:TheLOCK#outputpinenablestheCPUtoprevent
theotherbusmastersfromgainingthecontrolofthesystem
bus.
•NA#:Thenextaddressinputpin,ifactivated,allowsaddress
pipelining,during80386buscycles

58. ADS#:Theaddressstatusoutputpinindicatesthattheaddressbus
andbuscycledefinitionpins(W/R#,D/C#,M/IO#,BE0#toBE3#)
arecarryingtherespectivevalidsignals.
•READY#:ThereadysignalsindicatestotheCPUthattheprevious
buscyclehasbeenterminatedandthebusisreadyforthenext
cycle.ThesignalisusedtoinsertWAITstatesinabuscycleandis
usefulforinterfacingofslowdeviceswithCPU.
•VCC:Thesearesystempowersupplylines.
•VSS:Thesereturnlinesforthepowersupply.

59. BS16#:Thebussize–16inputpinallowstheinterfacingof16bit
deviceswiththe32bitwide80386databus.Successive16bitbus
cyclesmaybeexecutedtoreada32bitdatafromaperipheral.
•HOLD:Thebusholdinputpinenablestheotherbusmastersto
gaincontrolofthesystembusifitisasserted.
•HLDA:Thebusholdacknowledgeoutputindicatesthatavalid
busholdrequesthasbeenreceived.
•BUSY#:ThebusyinputsignalindicatestotheCPUthatthe
coprocessor(80387)isbusywiththeallocatedtask.

60. ERROR#:TheerrorinputpinindicatestotheCPUthatthe
coprocessorhasencounteredanerrorwhileexecutingits
instruction.
•PEREQ:Theprocessorextensionrequestoutputsignalindicates
totheCPUtofetchadatawordforthecoprocessor.
•INTR:Thisinterruptpinisamaskableinterrupt,thatcanbe
maskedusingtheIFoftheflagregister.
•NMI:Avalidrequestsignalatthenon-maskableinterruptrequest
inputpininternallygeneratesanon-maskableinterruptoftype2.
Signal.

61. RESET: A high at this input pin suspends the current operation and
restart the execution from the starting location.
• N/C : No connection pins are expected to be left open while
connecting the 80386 in the circuit.

62. Quiz Time
1) 80386 Can access -------------memory banks
a)2
b)3
c)4
d)1

63. 1) 80386 Can access -------------memory banks
a)2
b)3
c)4
d)1

64. 2) 80386DX has --------bit data bus and --------bit address bus.
a)32 & 30
b)32 & 16
c)16 & 32
d)32 & 32

65. 2) 80386 has --------bit data bus and --------bit address bus.
a)32 & 30
b)32 & 16
c)16 & 32
d)32 & 32

66. Architecture of 80386
Central processing unit
Memory management unit
Bus interface unit

67. The Internal Architecture of 80386 is divided into 3 main sections.
1. Central processing unit(CPU)
a. Execution Unit
b. Instruction Unit
2. Memory management unit(MMU)
a. Segmentation Unit
b. Paging Unit
3. Bus interface unit(BIU)

68. 1. Central processing unit(CPU)
Execution Unit:
–Ithas8generalpurposeand8specialpurposeregisterswhich
eitherhandlesdataoraddresses.
–Ithas64-bitbarrelshifter(Abarrelshifterisadigitalcircuitthat
canshiftadatawordbyaspecifiednumberofbitswithouttheuseofany
sequentiallogic)whichincreasesthespeedofallshift,rotate,multiply
anddivideoperations.
–Themultiply/dividelogicimplementsthebit-shift-rotate
algorithmstocompletetheoperationsinminimumtime(for
example32bitmultiplicationisdonein1µs)

70. •Executionreadsthedecodedinstructionfromtheinstructionqueueand
performstheoperationsthatarespecified.
•Duringtheexecutionofaninstruction,itrequeststhesegmentandpage
unitstogenerateoperandaddressesandthebusinterfaceunitto
performreadorwritebuscyclestoaccessdatainmemoryorI/Odevices.
•Instruction Unit:
–It decodes the opcode bytes received from the 16-byte instruction
queue and arranges them into a 3-decoded instruction queue.
–After decoding it is passed to control section for deriving necessary
control signals.

71. Central Processing Unit

72. Memory Management Unit
•MMU consists of a segmentation unit and paging unit.
•Segmentation Unit:
–Itallowstheuseoftwoaddresscomponents-segmentandoffset–
forrelocabilityandsharingofcodeanddata.
–Itallowsamaximumsegmentsizeof4GB.
–Itprovidesa4-levelprotectionmechanismforprotectingand
isolatingsystem’scodeanddatafromthoseofapplicationprogram.

73. –ThelimitandattributePLA(ProgrammableLogicalArray)checks
segmentlimitsandattributesatsegmentleveltoavoidinvalidaccesses
tocodeanddatainmemorysegment.
•PagingUnit
–Itorganizesphysicalmemoryintermsofpagesof4KBsize.
–Itworksunderthecontrolofsegmentationunit.
–Itconvertslinearaddressesintophysicaladdresses.
–ThecontrolandattributePLAchecksprivilegesatpagelevel.

74. Checks the privileges
at the page level

75. Bus Interface Unit
•Ithasaprioritizertoresolvethe
priorityofvariousbusrequests.
Thiscontrolstheaccessofthebus.
•Theaddressdriverdrivesthebus
enableandaddresssignalsA
2–A
31.
•Thepipeline/bussizeunithandles
thecontrolsignalsforpipeliningand
dynamicbussizingunits.
•Thedatabuffersinterfacethe
internaldatabuswithsystembus.
https://www.youtube.com/watch?v=Hn06bfyLO -c
https://www.youtube.com/watch?v=BNVwF3w7M5E
https://www.youtube.com/watch?v=tSw6NLBKRZY

76. Quiz Time
1) 80386 Architecture is divided in ---------main sections
A) 4
B) 3
C) 2
D) 5

77. 1) 80386 Architecture is divided in ---------main sections
A) 4
B) 3
C) 2
D) 5

78. 2) 80386 organizes physical memory in terms of pages of -----------------size.
a) 4 GB
b) 32 KB
c) 4 KB
d) 4 Byte

79. 2) 80386 organizes physical memory in terms of pages of -----------------size.
a) 4 GB
2) 32 KB
c) 4 KB
d) 4 Byte

80. •The Intel 386 DX has 32 register resources in the following categories:
–General Purpose Registers
–Segment Registers
–Instruction Pointer and Flags
–Control Registers
–System Address Registers
–Debug Registers
–Test Registers

81. General Purpose Registers
•Holddataoraddressvalues.
•Itsupportsdataof1,8,16,32and64bits.
•32-bitregisters(8):EAX,EBX,ECX,EDX,ESI,EDI,EBP,andESP.
•Theleastsignificant16bitsoftheregisterscanbeaccessedasin
8086withnamesoftheregistersAX,BX,CX,DX,SI,DI,BP,andSP.

82. •When accessed as a 16-bit operand, the upper 16 bits of the register
are neither used nor changed.
•8-bit operations can be performed with AL, BL, CL and DL registers.
•The higher bytes are AH, BH, CH and DH.
•The individual byte accessibility offers flexibility for data operations.

84. Segment Registers
•Segment register(6) − 16 bitsCS, DS, SS , ES , FS & GS etc.
•It holds the addresses of instructions and data in memory,
which are used by the processor to access memory locations.
•The segment registers are
–CS indicates the current code segment
–SS indicates the current stack segment
–DS, ES, FS and GS indicate four current data segments.

86. •Itisa32-bitregisternamedEIP.
•EIPholdstheoffset/addressofthenextinstructiontobeexecuted.
•Theoffsetisalwaysrelativetothebaseofthecodesegment(CS).
•Thelower16bitsofEIPcontainthe16-bitinstructionpointernamedIP,
whichisusedby16-bitaddressing.

87. Quiz Time
1)General Purpose Registers supports -----------bit/bits data size
a)1
b)8
c)64
d)All the above

88. 1)General Purpose Registers supports -----------bit/bits data size
a)1
b)8
c)64
d)All the above

89. 2) In 80386, segment registers are ---------of ----------bit size each.
a)6 & 8
b)6 & 16
c)8 & 8
d)8 & 16

90. 2) In 80386, segment registers are ---------of ----------bit size each.
a)6 & 8
b)6 & 16
c)8 & 8
d)8 & 16

91. 32 bit Flag Register
•Bit 17 (VM Bit, Virtual Mode):
–VM bit is set to work in Virtual 8086 mode
When VM flag is set, 80386 switches from protected mode to virtual 8086 mode.
•Bit 16 (RF Bit, Resume Flag):
–RF flag is used with debug register.
–When RF is set, debug fault need to be ignored on the next instruction.
–RF is then automatically reset after every instruction
•Bit 15 : Reserved

92. •Bit 14 (NT Bit, Nested Task):
–This flag applies to Protected Mode.
–NT is set to indicate that the execution of this task is nested within
another task.
–If set, it indicates that the current nested task's Task State Segment (TSS)
has a valid back link to the previous task's TSS.
•Bit 13,12 (IOPL Bit, Input/output Privilege):
–MaximumCPL(currentprivilegelevel)valuepermittedtoexecuteI/O
instructionswithoutgeneratinganexception13faultorconsultingtheI/O
PermissionBitmap.

93. •Bit 11 (OF Bit, Overflow Flag):
–OF is set if the operation resulted in a signed overflow.
•Bit 10 (DF Bit, Direction Flag):
–DF defines whether ESI/EDI registersdecrement or increment during the
string instructions.
–increment occurs ifDF is reset.
–decrement occurs if DF isset.

94. •Bit 9 (IF Bit, Interrupt Enable Flag):
–When IF =1 the processor allows recognition of external interrupts on
INTR pin.
•Bit 8 (TF Bit, Trap Enable Flag):
–When TF =1 the processor enables the single step mode for debugging.
•Bit 7 (SF Bit, Sign Flag):
–SF is set if the high-order bit of the result isset, it is reset otherwise.

95. •Bit 6 (ZF bit, Zero Flag):
–ZF is set if all bits of the result are 0.
•Bit 4 (AF Bit, Auxiliary Carry Flag):
–The Auxiliary Flag is used to simplify the additionand subtraction of packed
BCD numbers.
–AF is set if the operation resulted in acarry out of bit 3 (addition) or a
borrow into bit3 (subtraction). Otherwise AF is reset.
–AF is only for bit 3.

96. •Bit 2 (PF Bit, Parity Flag):
–PF is set for even parity ( i.e. 00111001 even parity).
•Bit 0 (CF Bit, Carry Flag):
–CF is set for 8, 16 or 32-bit operations if it results in a carry out of
(addition), or a borrow into (subtraction) the high-order bit.

98. Six Conditional Flags
◦Carry Flag (CF)
◦Parity Flag (PF)
◦Auxiliary Flag( AF)
◦Zero Flag (ZF)
◦Sign Flag (SF)
◦Overflow Flag (OF)
Three Control Flags
◦Interrupt Flag (IF)
◦Trap Flag (TF)
◦Direction Flag (DF)
Four System Flags
◦Input/output privilege level (IOPL)
◦Nested Task (NT)
◦Resume Flag (RF)
◦Virtual Mode Flag (VM)

99. Quiz Time
1) In 80386, 32 bit Flag Register _________ bits are reserved for Intel.
a)15
b)14
c)16
d)17

100. 1) In 80386, 32 bit Flag Register _________ bits are reserved for Intel.
a)15
b)14
c)16
d)17

101. 2 ) In 80386 , _________ bit is used for virtual mode.
a)15
b)14
c)16
d)17

102. 2 )In 80386 , _________ bit is used for virtual mode.
a)15
b)14
c)16
d)17

103. 3 ) In 80386 , there are _________ system flags.
a)5
b)4
c)6
d)3

104. 3 )In 80386 , there are _________ system flags.
a)5
b)4
c)6
d)3

105. Control Registers
•Intel 386 DX has 4 control registers (CR0, CR1 ,CR2 & CR3) of 32 bits to hold
machine state of a global nature.
•These registers along with System Address Registers hold machine state that
affects all tasks in the system.
•To access Control Registers, load and storeinstructions are defined.
•CR0 contains 6 defined bits for control and status purposes.

106. •The low-order 16 bits of CR0 is defined as Machine Status Word.
•To operate only on the low-order 16-bits of CR0, LMSW and SMSW
instructions are usedfor load and store respectively.
•For 32-bit operations the system should use MOV CR0, Reginstruction.

107. •Bit 31 (PG Bit, Paging Enable) : The PG bit is set to enable the on-chip paging
unit.
•Bit 4 (Reserved) : This bit is reserved by Intel.
•Bit 3 (TS Bit, Task Switched) : TS is automatically set whenever a task switch
operation is performed.
•Bit 2 (EM Bit, Emulate Coprocessor) :The EM bit indicates whether
coprocessor functions are to be emulated.
•Bit 1 (MP Bit, Monitor Coprocessor) :The EM and MP flags of CR0 control
how the processor reacts to coprocessor instructions.
•TheMOVinstruction can be executed only at privilege level zero (OS
level).

108. •Bit 0 (PE Bit, Protection Enable) :
–PE =1, enable the Protected Mode.
–If PE =0, processor operates in Real Mode.
Trap-and-emulate isa technique used by the virtual machine to emulate privileged
instructions and registers.
TheEMandMPflagsofCR0controlhowtheprocessorreactsto
coprocessorinstructions.TheEMbitindicateswhether
coprocessorfunctionsaretobeemulated.
TheMP(monitorcoprocessor)bitindicateswhethera
coprocessorisactuallyattachedORNOT.
TheEMandMPflagscanbechangedwiththeaidof
aMOVinstruction

109. •CR1 is reserved for use in future Intel processors
CR2
•CR2 holds the 32-bit linear address that caused the last page fault detected.
i.e. the processor stores in CR2 the linear address that triggers the fault

110. CR3 : Page Directory Base Address
•CR3 contains the physical base address of the page directory table.
•The Intel 386 DX page directory table is always page-aligned (4 Kbyte-aligned).
•Thus the lowest twelve bits of CR3 are ignored (12 bits).
11

112. 1)In 80386, ------control register is used for page fault linear
address.
a) CR0
b) CR1
c) CR2
d) CR3
Quiz Time

113. 1)In 80386, ------control register is used for page fault linear
address.
a) CR0
b) CR1
c) CR2
d) CR3

114. 2) In 80386, ------bits of CR0 register are used while other bits are
reserved.
a) 5
b) 4
c) 6
d) 3

115. 2) In 80386, ------bits of CR0 register are used while other bits are
reserved.
a)5
b) 4
c) 6
d) 3

116. 3) --------bits is the size of Page Directory Base Register in CR3.
a)18
b) 20
c) 22
d) 24

117. 3) --------bits is the size of Page Directory Base Register in CR3.
a)18
b) 20
c) 22
d) 24

118. 4)In 80386, ----------is the size of Machine Status Word (MSW)
a)8
b)16
c)18
d)17

119. 4)In 80386, ----------is the size of Machine Status Word
a)8
b)16
c)18
d)17

120. System Address Registers
•Four special registers are defined to reference the tables.
•These tables or segments are:
–GDT (Global Descriptor Table)
–IDT (Interrupt Descriptor Table)
–LDT (Local Descriptor Table)
–TSS (Task State Segment)
•The addresses of these tables and segments are stored in special registers, the
System Address and System Segment Registers respectively.
•These registers are named GDTR, IDTR, LDTR and TR.

121. The Global Descriptor Table
GDTisadatastructureusedbyIntelx86-familyprocessors
startingwiththe80286inordertodefinethecharacteristicsof
thevariousmemoryareasusedduringprogramexecution,
includingthebaseaddress,thesize,andaccessprivilegeslike
executabilityandwritability.
GDTcontainsdescriptorsofallthetasksinasystem.
GDTcontainanytypeofsegmentdescriptorexceptinterrupt
andtrapdescriptor.

122. What is an LDT?
TheLocalDescriptorTableisalistofdescriptorsforthecurrent
program.
ItisdistinctfromtheGDTinanumberofrespectsi.e.oneand
manyrespectively.
LDTcannotholdmanytypesofdescriptors;
ItisonlyaccessiblebyTasks/threadswiththesameLocal
DescriptorTableRegister(LDTR)value.

123. GDTR and IDTR
•These registers hold:
–16-bit limit
–32-bit linear base address and

124. LDTR and TR
•These registers hold 16-bit selector for
–LDT (Local Descriptor Table )descriptor and
–TSS ( Task State Segment )descriptor
•Since they are task specific, they are defined by selector values stored in
system segment registers.

125. System Segment Registers

126. How Segment Descriptor is accessed?
Requested Privilege Level (RPL)
(Bits 0and 1) —Specifiestheprivilegelevel of
theselector.

127. RealMode ProtectedMode
-Doesnotsupportvirtual
addressspace
-Givesvirtualandphysical
addressspace
-DoesnotsupportLDTandGDT
-Dosenotsupportprotection
mechanism and multi
programmingenvironment
-It supports protection
mechanism and multi
programmingenvironment
Difference between real mode and protected mode of 80386?
Real mode hassame base architectureas that of 8086, but allows
access to the 32-bit register set of 80386.
...
-Supports LDT and GDT
https://www.youtube.com/watch?v=eDrp2n2JDr8

128. Quiz Time
1)GDT contains descriptors of ---------tasks in a system.
A)2
B)8
C)16
D)All

129. 1)GDT contains descriptors of ---------tasks in a system.
A)2
B)8
C)16
D)All

130. 2) -------bits is the size of GDTR/IDTR
A)32
B)24
C)8
D)48

131. 2) -------bits is the size of GDTR/IDTR
A)32
B)24
C)8
D)48

132. 3) To select LDT/GDT --------bit is used in segment register
a)1
b)2
c)3
d)4

133. 3) To select LDT/GDT --------bit is used in segment register
a)1
b)2
c)3
d)4

134. 4)In 80386, ----------is the size of descriptor register
a)4 byte
b)2 byte
c)8 byte
d)1 byte

135. In 803686, ----------is the size of descriptor register in 803686
a)4 byte
b)2 byte
c)8 byte
d)1 byte

136. Segment selector
InRealmode16bitsegmentregistersholdthestartingaddressof
thesegment.
InProtectedmodethesesegmentregistersareusedassegment
selectorbecauseitselectsasegmentdescriptor.
Segmentdescriptorisastructureof8bytes(64bits)thatisusedto
describeandlocatesegmentpresentinmemoryfromdescriptor
table.
Selectorisusedtoindex(point)adescriptorfromthetableof
descriptors.

137. Hence
Everymemoryaccesswhichaprogramcanperformalways
goesthroughasegmentselector.
Inordertoreferenceasegment,aprogrammustuseitsindex
insidetheGDTortheLDT.
Suchanindexiscalledasegmentselector(orselector).
Theselectormustgenerallybeloadedintoasegmentregisterto
beused.

138. Interrupt Descriptor Table & IDTR
IDTcontainsgroupofdescriptorsthatdefinetheinterruptsor
exceptionhandlingroutines.
For80386toworkinprotectedmodeatleastoneIDTneedstobe
defined.
TheIDTcontainsthedescriptorswhichpointtothelocationofup
to256interruptserviceroutine(ISR).
EveryinterruptusedbythesystemmusthaveanentryintheIDT.

139. 16

140. However,80386supports3operatingmodes:real,protectedand
virtualrealmode.
Initiallythe80386wasbootedinrealmode.
Protectedmodeonthe386offerstheprogrammerbetter
protectionandmorememorythanonthe286.
386alsosupportsathirdmode,Virtual8086(V86)mode.
InV86mode,the386operatesinprotectedmodebutallowsto
useasimulatedreal-modeenvironment.

141. Quiz Time
1)Segment descriptor is a structure of ------------------bytes
A)4
B)2
C)8
D)16

142. 1)Segment descriptor is a structure of ------------------bytes
A)4
B)2
C)8
D)16

143. 2) IDT contains the descriptors which point to the location of
up to -----------interrupt service routine.
a)64
b)128
c)256
d)32

144. 2) IDT contains the descriptors which point to the location of up
to -----------interrupt service routine.
a)64
b)128
c)256
d)32

145. Data Types
The Intel 386 DX supports all of the data types commonly
used in high level languages:
Bit: A single bit quantity.
Bit Field: A group of up to 32 contiguous bits,
which spans a maximum of four bytes.

146. Bit String: A set of contiguous bits, on the Intel386 DX bit strings can
be up to 4 gigabits long.
Byte: A signed
8-bit quantity
(range -128 to+127)

147. •Unsigned Byte: An unsigned 8-
bit quantity.
(range 0 to 255)
•Integer (Word): A signed 16-bit
quantity.
(-32768 to 32767)
•Long Integer (Double Word):
–A signed 32-bit quantity.
(-2.147*10
9
to + 2.147*10
9 )

148. •Unsigned Integer (Word): An
unsigned 16-bit quantity.
(0 to 65535)
•Unsigned Long Integer (Double
Word): An unsigned 32-bit
quantity.(0 to 4294967295)

149. •Signed Quad Word: A signed 64-bit quantity.
•Unsigned Quad Word: An unsigned 64-bit quantity.

150. Offset:A16-or32-bitoffsetonlyquantitywhichindirectly
referencesanothermemorylocation.

151. •Pointer:Afullpointerwhichconsistsofa16-bit
segmentselectorandeithera16-or32-bitoffset.
16 bits 32 bits

152. Char:A byte representation of an ASCII Alphanumeric or control
character.

153. Quiz Time
1)Signed quad word data type is having --------bit size.
a)32
b)128
c)24
d)64

154. Signed quad word data type is having --------bit size.
a)32
b)128
c)24
d)64

155. Data Addressing Modes
The 80386 memoryaddressing modesprovide flexible access to
memory, allowing you to easily access variables, arrays, records,
pointers, and other complex data types.
Following figure illustrates the MOV instruction and defines the direction
of data flow

156. Immediate Addressing
•Term immediateimplies that data immediately follow the hexadecimal
opcode in the memory.
–immediate data are constant data
•Immediate addressing operates upon a byte or word of data.
•Figure shows the operation of a MOV EAX,13456H instruction.
opcode Operand
(Opcodeis a part of the instruction that tells the processor what should be done.Operandis a part of the
instruction that contains the data to be acted on, or the memory location of the data in a register)
Instruction

157. Figure The operation of the MOV EAX,3456H instruction.
This instruction copies the immediate data 13456H into EAX.
The source data overwrites the destination data.

158. Register Addressing Mode
•Themostcommonformofdataaddressing.
•Themicroprocessorcontainsthese8-bitregisternamesusedwith
registeraddressing:AH,AL,BH,BL,CH,CL,DH,andDL.
•16-bitregisternames:AX,BX,CX,DX,SP,BP,SI,andDI.

159. •In 80386 & above, extended 32-bit register names are: EAX,
EBX, ECX, EDX, ESP, EBP, EDI, and ESI.
•It is important for instructions, to use registers which are the
same size.
–nevermix an 8-bit \with a 16-bit register, an 8-or a 16-bit
register with a 32-bit register
–this is not allowed by the microprocessor and results in an
error when assembled
for example MovEAX, DX

160. FigureTheeffectofexecutingtheMOVBX,CXinstruction
atthepointjustbeforetheBXregisterchanges.
Notethatonlytherightmost16bitsofregisterEBXchange.
15
31

161. •FigureshowstheoperationoftheMOVBX,CXinstruction.
•Thesourceregister’scontentsdonotchange.
thedestinationregister’scontentsdochange
•Thecontentsofthedestinationregisterordestinationmemory
locationchangeforallinstructionsexcepttheCMPandTEST
instructions.
•TheMOVBX,CXinstructiondoesnotaffecttheleftmost16bitsof
registerEBX.

162. The remaining modes provide a mechanism for specifying the
effective address (EA)of an operand.
The linear address consists of two components:
The segment base address and
An effective address.

163. The effective address is calculated by using four address elements:
DISPLACEMENT: An 8 bit or 32-bit immediate value
BASE: The contents of any general purpose register. It point to
the start of the local variable area.
INDEX: The index registers are used to access the elements of an
array, or a string of characters.
SCALE: The index register's value can be multiplied by a scale
factor, either 1, 2, 4 or 8.
Scaled index mode is especially useful for accessing arrays or
structures.

164. Combinationsofthese4components makeupthe
additionaladdressingmodes.
Theeffectiveaddress(EA)ofanoperandiscalculated
accordingtothefollowingformula:
EA=BaseRegister+(IndexRegister*Scaling)+
Displacement.

165. Effective address (EA) calculation can be shown as follows:

166. Direct Addressing Modes
•Appliedtomanyinstructionsinatypicalprogram.
•Twobasicformsofdirectdataaddressing:
–directaddressing,whichappliestoaMOVbetweena
memorylocationandAL,AX,orEAXregisters.
–displacementaddressing,whichappliestoalmostany
instructionintheinstructionset.
•Addressisformedbyaddingthedisplacementtothedefault
datasegmentaddressoranalternatesegmentaddress.

167. Figure The operation of the MOV AL,[1234H] instruction
when DS=10000H .
•This instruction transfers a copy contents of memory location 11234H
into AL.
–the effective address is formed by adding
1234H (the offset address) and 10000H

168. Register Indirect Addressing Mode:
•Allows data to be addressed at any memory location through
an offset address held in any of the following registers: BP, BX, DI,
and SI.
•In addition, 80386 and above processors allow register indirect
addressing with any extended register except ESP.

169. Indirect addressing often allows a program to refer to tabular
data located in memory.
Figure5showsthetableandtheBXregisterusedto
sequentiallyaddresseachlocationinthetable.
To accomplish this task, load the starting location of the table
into the BX register with a MOV immediate instruction.
After initializing the starting address of the table, use register
indirect addressing to store the 50 samples sequentially.

170. Figure 4The operation of the MOV AX,[BX] instruction when BX =
1000H and DS = 0100H. Note that this instruction is shown after the
contents of memory are transferred to AX.
(100*10)

171. Base-Plus-Index Addressing
•Similartoindirectaddressingbecauseitindirectlyaddresses
memorydata.
•Thebaseregisteroftenholdsthebeginninglocationofamemory
array.
–the index registerholdsthe relativeposition
ofanelementinthearray.
–wheneverBPaddressesmemorydata,boththestacksegment
registerandBPgeneratetheeffectiveaddress

172. •Figure 6 shows how data are addressed by the
MOV DX,[BX + DI] instruction when the microprocessor operates
in the real mode.
•The Intel assembler requires this addressing mode appear as
[BX][DI] instead of [BX + DI].
•The MOV DX,[BX + DI] instruction is MOV DX,[BX][DI] for a
program written for the Intel ASM assembler.

173. Figure An example showing how the base-plus-index addressing
mode functions for the MOV DX,[BX + DI] instruction.
Notice that memory address 02010H is accessed because DS=0100H,
BX=1000H and DI=0010H.

174. scale

175. (Accumulator)

176. Memory Based Addressing Modes Register Based Addressing Modes
The operand is present in memory and its address is given in
the instruction itself. This addressing mode is taking proper
advantage of memory address, e.g., Direct addressing mode
An operand will be given in one of the register and register number will
be provided in the instruction . With the register number present in
instruction, operand is fetched, e.g., Register mode
The memory address specified in instruction may give the
address where the effective address is stored in the memory.
In this case effective memory address is present in the
memory address which is specified in the instruction, e.g.,
Indirect Addressing Mode
The register contains the address of the operand. The effective address
can be derived from the content of the register specified in the
instruction. The content of the register might not be the effective
address. This mode takes full advantage of registers, e.g., Register
indirect mode
The content of base register is added to the address part of
the instruction to obtain the effective address. A base register
is assumed to hold a base address and the address field of
the instruction gives displacement relative to the base
address, e.g., Base Register Addressing Mode
If we are having a table of data and our program needs to access all
the values one by one we need something which decrements the
program counter/or any register which has base address. Though in this
case register is basically decreased, it is register based addressing
mode, e.g., In Auto decrements mode
The content of the index register is added to the address part
that is given in the instruction to obtain the effective address.
Index Mode is used to access an array whose elements are in
successive memory locations, e.g., Indexed Addressing Mode
If we are having a table of data and our program needs to access all
the values one by one we need something which increment the
program counter/or any register which has base address, e.g., Auto
increment mode
The content of program counter is added to the address part
of the instruction in order to obtain the effective address. The
address part of the instruction in this case is usually a signed
number which can be either positive or negative, e.g.,
Relative addressing mode
Instructions generally used for initializing registers to a constant value is
register based addressing mode, and this technique is very useful
approach, e.g., Immediate mode.

177. CISC&RISC(ComplexInstructionSetComputer&ReducedInstruction
SetComputer)
CISC
Intheearlydaysofcomputerhistory,mostcomputerfamiliesstartedwithan
instructionsetwhichwassimple.
Themainreasonforbeingsimplethenwasthehighcostofhardware/technology
anduse.
Thehardwarecosthasdroppedandthesoftwarecosthasgoneupsteadilyinthe
pastdecades.
Furthermore,thesemanticgapbetweenHLLfeaturesandcomputerarchitecture
haswidened.
Nowadaysmoreandmorefunctionswerebuiltintothehardware,makingthe
instructionsetlargeandcomplex.

178. Thegrowthofinstructionsetswasalsoincreasedbecauseofthepopularityof
usingmicrocodesinsomeprocessorsforspecial-purposeapplications.
AtypicalCISCinstructionsetcontainsapproximately120to350instructions
usingvariableinstruction/dataformats,usesasmallsetof8to24general-
purposeregisters(GPRs).
ManyHLLstatementsaredirectlyimplementedinhardware/firmwareina
CISCarchitecture.
Thismaysimplifythecompilerdevelopment,improveexecutionefficiency,
andallowanextensionfromscalarinstructionstovectorinstructions.

179. RISC
WestartedwithRISCinstructionsetsandgraduallymovedtoCISCinstructionsets
duringthe1980s.
AftertwodecadesofusingCISCprocessors,computerusersbegantoreevaluate
theperformancerelationshipbetweeninstruction-setarchitectureandavailable
hardware/softwaretechnology.
Frommanyyearscomputerscientistsrealizedthatonly25%oftheinstructionsofa
complexinstructionsetarefrequentlyusedabout95%ofthetime.
Itmeansabout75%ofhardware-supportedinstructionsoftenarenotusedatall.
Thenwhyshouldwewastevaluablechipareaforrarelyusedinstructions?

180. Itmaybemoreadvantageoustoremovethemcompletelyfromthehardware
andrelyonsoftwaretoimplementthem.
Evenifthesoftwareimplementationisslow,thenetresultwillbestillaplus
duetotheirlowfrequencyofuse.
Pushingrarelyusedinstructionsintosoftwarewillvacatechipareasfor
buildingmorepowerfulRISCorsuperscalarprocessors,evenwithon-chip
cachesorfloating-pointunits.
ARISCinstructionsettypicallycontainslessthan100instructionswithafixed
instructionformat(32bits).
WhereasCISCprocessoruses120to350instructions

181. Onlythreetofivesimpleaddressingmodesareused.
Mostinstructionsareregister-based.
Memoryaccessisdonebyload/storeinstructionsonly.
Alargeregisterfileisusedtoimprovefastcontextswitchingamongmultiple
programs,andmostinstructionsexecuteinonecyclewithhardwiredcontrol.
Becauseofthereductionininstruction-setcomplexity(numberofinstructions),
theentireprocessorisimplementableonasingleVLSIchip.

182. TheresultingbenefitsincludeahigherclockrateandalowerCPI(Cyclesper
instruction),whichleadtohigherMIPSratingsasreportedoncommercially
availableRISC/superscalarprocessors.

183. Cycles per instruction

184. Intel core i9 processor
Technical Specifications of Intel core i9
Performance
Intel® Thermal Velocity Boost Frequency
5.20 GHz
# of Cores
10
# of Threads
20 (EachCPU corecan have twothreads)
Processor Base Frequency
3.60 GHz
Max Turbo Frequency
5.20 GHz
(Thermal Velocity Boost allows these CPUs to hit even higher boost speeds than its
typical all-core turbo boost.)

185. Cache
20 MB
Bus Speed
8 GT/s (gigatansfer/second)
Memory Specifications
Max Memory Size (dependent on memory type)
128 GB
Memory Types
DDR4-2933 (double data rate fourth generation)
Max # of Memory Channels
2
Max Memory Bandwidth
45.8 GB/s
(The number ofthreadsdepends on the number ofcoresin yourCPU. EachCPU
corecan have twothreads. So a processor with twocoreswill have fourthreads.
Threads are virtual codes which divides the physical core of CPU into virtual
multiple cores)

186. List of Intel Core i9 processors Land grid array(LGA) for interface
(Thermal
Power) power
consumption