Computer organization and architecture|KTU

Computer organization and architecture

1. Computer Organization and Architecture
CST 202

7. What is the difference between Computer
Architecture & Computer Organization
•Computer Organization
❑Computer organization describes the internal properties of the
computer as viewed from the perspective of the hardware engineer.
❑ Computer organization refers to the operational units and their
interconnections that realize the architectural specifications.
Computer Architecture
❑The overall design or structure of a computer system, including the
hardware and the software required to run it, especially the internal
structure of the microprocessor.
❑ Computer architecture describes the properties of the computer as
viewed from the perspective of the programmer.

8. Functional units of a computer
● The computer system is divided into five
separate units for its operation.
● Input Unit.
● ALU.
● Control Unit.
● Memory Unit.
● Output Unit.

10. 10
Functional units of a computer
I/O Processor
Output
Memory
Input
Control
Arithmetic
& Logic
Instr1
Instr2
Instr3
Data1
Data2
Input unit accepts
information:
•Human operators,
•Electromechanical devices (keyboard)
•Other computers
Output unit sends
results of processing:
•To a monitor display,
•To a printer
Arithmetic and logic unit(ALU):
•Performs the desired
operations on the input
information as determined
by instructions in the memory
Control unit coordinates
various actions
•Input,
•Output
•Processing
Stores
information:
•Instructions,
•Data

11. Input unit
•The method of feeding data and programs to a computer is accomplished by an
input device.
•Computer input devices read data from a source, such as
magnetic disks, and translate that data into electronic impulses [ADC] for transfer
into the CPU.
•Some typical input devices are a keyboard, a mouse, scanner, etc.
Joysticks, trackballs, mouse, scanners etc are other input devices.
- Interfaces with input devices
- Accepts binary information from the input devices.
- Presents this binary information in a format expected by the computer.
- Transfers this information to the memory or processor.

12. Output unit
•Computer output devices converts the electronic impulses [DAC] into
human readable form.
•Output unit sends processed results to the outside world.
- Interface with output devices.
- Accept processed results provided by the computer in specific binary form.
- Convert the information in binary form to a form understood by an output
device.
•Examples: Display screens, Printers, plotters, synthesizers, high-tech
blackboards etc.

13. Memory Unit (MU)
Memory unit stores instructions and data. It is basically to two types
Primary memory
Secondary memory
•Primary memory: -
Fast Memory that operates at electronic speeds . The memory contains a large number of
semiconductor storage cells,each capable of storing one bit of information.
❑Processor reads instructions and reads/writes data from/to the memory during the execution
of a program.
◆ instructions and data could be fetched one bit at a time.
◆Group of bits stored or retrieved at a time is termed as
“word”
◆Number of bits in a word is termed as the “word length”
of a computer.
❑In order to read/write to and from memory, a processor should know where to look:
◆“Address” is associated with each word location.

14. ❑Processor reads/writes to/from memory based on the memory address:
◆Access any word location in a short and fixed
amount of time based on the address.
◆Random Access Memory (RAM) provides fixed
access time independent of the location of the word.
◆The time required to access one word is called
memory access time.
◆Memory which is only readable by the user and
contents of which can’t be altered is called read only
memory (ROM) .
❑Memory and processor have to “communicate” with each other in order to read/write
information.
◆In order to reduce “communication time”, a small
amount of RAM is tightly coupled with the
processor. it is known as Cache.

15. ❑Primary storage of the computer consists of RAM units.
◆Fastest, smallest unit is Cache.
◆Slowest, largest unit is Main Memory.
❑Primary storage is insufficient to store large amounts of data and programs.
◆Primary storage can be added, but it is expensive.
❑Store large amounts of data on secondary storage devices:
◆Magnetic disks and tapes,
◆Optical disks (CD-ROMS).
◆Access to the data stored in secondary storage in
slower, but take advantage of the fact that some
information may be accessed infrequently.
❑Cost of a memory unit depends on its access time, lesser access time implies higher
cost.

16. Arithmetic Logical Unit (ALU)
❑Operations are executed in the Arithmetic and Logic Unit (ALU).
◆Arithmetic operations such as addition, subtraction.
◆Logic operations such as comparison of numbers.
❑In order to execute an instruction, operands need to be brought into the ALU from
the memory.
◆Operands are stored in general purpose registers
available in the ALU.
◆Access times of general-purpose registers are faster
than the cache.
❑Results of the operations are stored back in the memory or retained in the processor
for immediate use.

17. Control Unit
Functions of the Control Unit
•The primary role of the Control Unit is to orchestrate the activities of the
computer system to ensure instructions are executed in the correct sequence and
manner. Its key functions include:
•Acts like the supervisor seeing whether things are done in proper fashion.
•Control unit controls and coordinates the entire operations of the computer
system.
•The control unit determines the sequence in which computer programs and
instructions are executed. Things like processing of programs stored in the main
memory, interpretation of the instructions and issuing of signals for other units of
the computer to execute them.
•It also acts as a switch board operator when several users access the computer
simultaneously. Thereby it coordinates the activities of computer’s peripheral
equipment as they perform the input and output. Therefore it is the manager of
all operations.

18. Basic Operational Concepts
Connection Between the Processor and Memory
❑Program consisting of a list of instructions is stored in the
memory.
❑ Individual instructions are brought from the memory into
the processor, which executes the specified operations
Instruction Example

19. Basic Operational Concepts
Connection Between the Processor and Memory
❑Program consisting of a list of instructions is stored in the
memory.
❑ Individual instructions are brought from the memory into
the processor, which executes the specified operations.
❑Data to be used as operands are also stored in the memory.
Examples: - Add LOCA, R0
This instruction adds the operand at memory location LOCA,
to operand in register R0 & places the sum into register.
steps
1. First the instruction is fetched from the memory into
the processor.
2.The operand at LOCA is fetched and added to the
contents of R0
3.Finally the resulting sum is stored in the register R0

20. Basic Operational Concepts
Connection Between the Processor and Memory

21. Basic Operational Concepts
Connection Between the Processor and Memory
❑The instruction register (IR):- Holds the instructions that
is currently being executed.
❑The control circuits which generates the timing signals
that control the various processing elements involved in
executing the instruction.
❑The program counter(PC): This is another specialized
register that keeps track of execution of a program. It
contains the memory address of the next instruction to be
fetched and executed.

22. ❑There are n-general purpose registers R0 through Rn-1.
❑The other two registers which facilitate communication
with memory are: -
❑MAR – (Memory Address Register):- It holds the address of
the location to be accessed.
❑MDR – (Memory Data Register):- It contains the data to be
written into or read out of the addressed location.
Basic Operational Concepts
Connection Between the Processor and Memory

23. Typical Operating Steps (Fetch Cycle)
1.Programs reside in the memory & usually get these through the I/P unit.
2.Execution of the program starts when the PC is set to point at the first
instruction of the program.
3.Contents of PC are transferred to MAR and a Read Control Signal is sent
to the memory.
4.After the time required to access the memory elapses, the addressed
word is read out of the memory and loaded into the MDR.
5.Now contents of MDR are transferred to the IR & now the instruction is
ready to be decoded and executed.
6.If the instruction involves an operation by the ALU, it is necessary to
obtain the required operands.

24. Typical Operating Steps (Fetch Cycle)
6. When the operand has been read from the memory to the MDR, it is
transferred from MDR to the ALU.
7. After one or two such repeated cycles, the ALU can perform the desired
operation.
8. If the result of this operation is to be stored in the memory, the result is
sent to MDR.
9. Address of location where the result is stored is sent to MAR & a write
cycle is initiated.
10.The contents of PC are incremented so that PC points to the next
instruction that is to be executed.

25. Memory Location, Addresses, and Operation
⚫Memory consists of
many millions of storage
cells, each of which can
store a bit of
information having the
value 0 or1..
⚫Data is usually accessed
in n-bit groups called
word.
⚫n is called word length.
⚫The memory of a
computer can be
schematically
represented as a
collection of words
second word
first word
Figure 2.5. Memory words.
nbits
last word
ith word
•
•
•
•
•
•

26. Memory Location, Addresses, and Operation
⚫32-bit word length example
(b) Four characters
charactercharactercharacter character
(a) A signed integer
Sign bit: for positive numbers
for negative numbers
ASCIIASCIIASCIIASCII
32 bits
8 bits 8 bits 8 bits 8 bits
b
31
b
30
b
1
b
0
b
31
0=
b
31
1=
•••

27. Memory Location, Addresses, and Operation
⚫To retrieve information from memory, either for one word or
one byte (8-bit), addresses for each location are needed.
⚫A k-bit address memory has 2
k
memory locations, namely 0
– 2
k
-1, called memory space.
⚫24-bit addr memory: 2
24
= 16,777,216 = 16M (1M=2
20
)
⚫32-bit addr memory: 2
32
= 4G (1G=2
30
)
⚫1K(kilo)=2
10
⚫1T(tera)=2
40

28. Accessing numbers, characters and strings
Number
Number usually occupies one word. It can be accessed by
word address.
Character
 usually occupies one byte. By byte address
Strings
They are of variable length
Beginning of the string by giving the beginning byte
address which contains first character
Successive bytes contains successive characters
Termination?
Either by a special control character
Or a separate memory word location/ register containing
a number indicating the string length
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29. Memory Location, Addresses, and Operation
•It is impractical to assign distinct addresses to individual bit locations in
the memory.
•The most practical assignment is to have successive addresses refer to
successive byte locations in the memory is called byte-addressable
memory.
•Word alignment - Words are said to be aligned in memory if they begin
at a byte address that is a multiple of the number of bytes in a word.
•Byte locations have addresses - 0,1, 2, 3, etc …
•word length is 16 bits, the successive words are located at addresses -
0, 2, 4, 6, etc…
•word length is 32 bits, the successive words are located at addresses -
0, 4, 8,12, etc…

30. Big-Endian and Little-Endian Assignments
There are two ways that byte addresses can be assigned across words.
Big-Endian: lower byte addresses are used for the most significant bytes
of the word
Little-Endian: opposite ordering. lower byte addresses are used for the
least significant bytes of the word

31. Problems
1.A memory has 32-bit address and byte-addressable,
what is the size of the memory (in bytes)?
2.A memory has 24-bit address and word-addressable
with a word length of 32 bits, what is the size of the
memory (in bytes)?
3.A memory has 16-bit address and byte addressable.
Word length is 32 bits. How many words can we store
in such a memory?
Note: A memory with k-bit address
a) byte-addressable → 2
k
bytes
b) word-addressable → 2
k
words
(1G = 2
30
)
(1M = 2
20
)
(1K = 2
10
)

32. Answers
1.32-bit address, byte addressable memory
No of bytes = 2
32
= 2
30
x 2
2

= 4G bytes (1G = 2
30
)
2. 24-bit address, word addressable, 1Word =32 bits (4 bytes)
No of words = 2
24
= 2
20
x 2
4

No of bytes = No of words x (bytes/word)
= 2
20
x 2
4
x 2
2
(1 word = 4 bytes)


= 64M bytes (1M = 2
20
)
3. 16-bit address, byte addressable, 1Word =32 bits (4 bytes)
No of words = No of bytes / (bytes/word)
= 2
16
/ 2
2
= 2
10
x 2
6
/ 2
2
(1 word = 4 bytes)

= 16 K words (1K = 2
10
)

33. Memory Operations
•Both program instructions and data operands
are stored in the memory.
•Two basic operations involving the memory
are needed, namely, Read and Write.
•The Read operation transfers a copy of the
contents of a specific memory location tothe
processor. The memory contents remain
unchanged.

34. •To start a Read operation, the processor sends
the address of the desired location to the
memory and requests that its contents be
read.
•The memory reads the data stored at that
address and sends them to the processor.

35. •The Write operation transfers an item of information
from the processor to a specific memory location,
overwriting the former contents of that location.
•To initiate a Write operation, the processor sends the
address of the desired location to the memory,
together with the data to be written into that
location.
•The memory then uses the address and data to
perform the write.

36. Memory Operations
⚫Load (or Read or Fetch)
➢Copy the content
➢Memory content doesn’t change
➢Address → MAR, read from mem, content → MDR
➢Registers can be used
⚫Store (or Write)
➢Overwrite the content in memory
➢Address → MAR and Data → MDR, write to mem
➢Registers can be used

37. INSTRUCTIONS AND INSTRUCTION SEQUENCING
•A computer must have instructions capable of
performing four types of operations:
⚫Data transfers between the memory and the processor
registers
⚫Arithmetic and logic operations on data
⚫Program sequencing and control
⚫I/O transfers

38. Register Transfer Notation
⚫Identify a location by a symbolic name standing for its
hardware binary address.
⚫Name for the address of memory location (LOC,
PLACE,A,VAR2…)
⚫Processor register names may be(R0,R5)
⚫Contents of a location are denoted by placing square
brackets around the name of the location .
▪R1← [LOC]
▪R3 ← [R1] + [R2] this type of notation is known as Register
Transfer Notation (RTN).
▪Right hand side always denote a value,left handside is the
name of location where value is to be placed.

39. Assembly Language Notation
•We need another type of notation to represent machine
instructions and programs. For this, we use assembly
language.
•For eg, from memory location LOC to processor register
R1, is specified by the statement
Move LOC, R1
•The contents of LOC are unchanged by the execution of
this instruction, but the old contents of register R1 are
overwritten.

40. •The second example of adding two numbers
contained in processor registers R1 and R2
and placing their sum in R3 can be specified by the
assembly-language statement
Add R1, R2, R3
In this case, registers R1 and R2 hold the source
operands, while R3 is the destination.

41. ➢ Instruction :Instruction contains Opcode and Operand
•Opcode - which tells about the operation to be performed.
•Address field /Operand- designating a memory address of operand
or a processor register.
Basic Instruction Types

42. Instruction Types
⚫Three-Address Instructions: instruction contains memory
address of three operands.
(operation src1, src2,destination)
⚫ADD R1, R2, R3 ; R3 ← R1+ R2
⚫Two-Address Instructions
(operation src, destination)
⚫ADD R1, R2 ; R2 ← R1 + R2
⚫One-Address Instructions
( in arithmetic operations, a processor register called
accumulator is used)
⚫ADD B ; AC ← AC + M[B]
⚫LOAD A ; AC ← M[A] ; Load instruction copies the
content of memory location A into accumulator
⚫Store A ; Store instruction copies the content of accumulator
into memory location A
⚫PUSH X ; TOS ← M[X]

43. ⚫Zero-Address Instructions
• (all operands are defined implicitly, store operands in
pushdown stack)
⚫ ADD ; TOS ← TOS + (TOS – 1) (stack grows up)
(This operation has effect of popping the two top numbers from
stack, adding the numbers, and pushing the sum into the
stack)

44. ➢There are two phases of Instruction Execution
➢Instruction Fetch
➢Instruction Execution
Instruction Fetch:
The instruction is fetched from the memory location whose address is in
PC.This is placed in IR.
Instruction Execution:
Instruction in IR is examined to determine which operation is to be
performed.
Instruction Execution and Straight-Line Sequencing

45. Instruction Execution and Straight-Line Sequencing
•Consider task C = A + B, implemented as C←[A] + [B].
•Assume that the word length is 32 bits and the
memory is byte-addressable.
•The three instructions of the program
are in successive word locations, starting at location
i.
•Since each instruction is 4 bytes long, the second and
third instructions are at addresses i + 4 and i + 8.

46. Program execution Steps:
1.To begin executing a program, the address of first instruction
must be placed in PC.
2.The processor control circuits use the information in the PC to
fetch & execute instructions one at a time in the order of
increasing order. This is called Straight line sequencing .
3. During the execution of each instruction , the PC is
incremented by 4 to point the address of next instruction.
Thus, after the Move instruction at location i + 8 is executed, the
PC contains the value i + 12, which is the address of the first
instruction of the next program segment.

47. Instruction Execution and Straight-Line Sequencing

48. ⚫The Address of the memory
locations containing the n numbers
are symbolically given as
NUM1,NUM2…..NUMn.
⚫Separate Add instruction is used to
add each number to the contents of
register R0.
⚫After all the numbers have been
added,the result is placed in
memory location SUM.
Instruction Execution and Straight-Line Sequencing

49. Instruction Execution and Branching
•Consider the task of adding a list of n numbers.
•LOOP is a straight line sequence of
instructions executed as many times as needed.
•Assume that the number of entries in the list, n, is stored in memory
location N.
•Register R1 is used as a counter to determine the number of times
the loop is executed. Hence, the contents of location N are loaded
into register R1 at the beginning of the program.
•Then, within the body of the loop, the instruction Decrement R1
reduces the contents of R1 by 1 each time through the loop.
•Execution of the loop is repeated as long as the content of R1 is
greater than zero.

50. •Branch instructions loads a new address into
the program counter. As a result, the processor fetches
and executes the instruction at this new
address, called the branch target, instead of the
instruction at the location that follows the
branch instruction in sequential address order.
•A conditional branch instruction causes a branch only
if a specified condition is satisfied.
•If the condition is not satisfied, the PC is incremented in
the normal way, and the next
instruction in sequential address order is fetched and
executed.

51. ⚫Using loop to add ‘n’ numbers:
⚫Number of enteries in the list „n‟ is
stored in memory location N.
Register R1 is used as a counter to
determine the number of times the
loop is executed.
⚫Content location N are loaded into
register R1 at the beginning of the
program. It starts at location Loop
and ends at the instruction
Branch>0.During each pass, the
address of the next list entry is
determined and the entry is fetched
and added to R0.
⚫It reduces the contents of R1 by 1
each time through the loop.
⚫Branch >0 Loop A conditional
branch instruction causes a branch
only if a specified condition is
satisfied.
Instruction Execution and Branching

52. Condition codes
•The processor keeps track of instruction about the
results of various operations for use by subsequent
conditional branch instructions. This is
accomplished by recording the required information
in individual bits often called as conditional code
flags.
•These flags are usually grouped together in a special
processor register called the condition code register
or status register.

53. Condition Codes
⚫Condition-code bits are also called status bits or flag bits.
⚫Condition code flags =>condition code flags are set to 1 or cleared to 0,
depending on the result of the operation performed in the ALU.
⚫Four commonly used flags are
⚫N(negative) :Set to 1 if the result is negative; otherwise, cleared to 0
⚫Z(zero) : Set to 1 if the result is 0; otherwise, cleared to 0
⚫V(overflow): Set ot1 if arithmetic overflow occurs; otherwise, cleared to 0
⚫C(carry): Set to 1 if a carry-out results from the operation; otherwise,
cleared to 0
⚫

54. •Addressing mode -The ways in which the location of an operand is
specified in an instruction are referred to as addressing modes.
• Effective Address - is the actual location of an operand of an instruction.
•Opcode field - specifies the operation to be performed.
•Operand - data on which the operation is to be performed.
•operand(data) may be in accumulator, general purpose register or at some
specified memory location
Addressing Modes

55. Types of Addressing Modes
❖Register mode
❖Absolute/ Direct mode
❖Immediate mode
❖Indirect mode
❖Index mode
❖Base with index
❖Base with index and offset
❖Relative mode
❖Auto - increment mode
❖Auto - decrement mode

56. Register Addressing
•The operand is the contents of a processor register; the
name (address) of the register is given in the
instruction.
•EX:Move R1, R2
ADD R1, R2
Ea=R1
Effective Address (Ea) is the memory address used during an instruction to fetch
or store data.

57. Direct /Absolute Addressing
•The operand is in a memory location; the address of this
location is given explicitly in the instruction.
Ex:Move LOC, R2
Ea=loc
57

58. Immediate Addressing
•The operand is given explicitly in the instruction.
•Ex:Move #200,R0
• Add #6,R1
•Ea=value,200

59. Indirect Addressing
• The effective address of the operand is the contents of
a register or memory location whose address appears in
the instruction.
•We denote indirection by placing the name of register or
memory address given in the instruction in
parentheses().
•The register or memory location contains the address of
operand is called a pointer.
•Ex:Add (R1),R0
•Add (A),R0

60. ⚫Index mode – the effective address of the operand is
generated by adding a constant value to the contents of a
register.
▪X( Ri ) ; EA = [ Ri ] + X
Ri → Index register
X → constant given either as an explicit number or as a
symbolic name representing a numerical value.
▪Effective address= start address + displacement
▪(Index register holds address of a new location and value
of X defines an offset (displacement)
▪Ex:Add 20(R1),R2

Indexed / Displacement Addressing

61. Indexed / Displacement Addressing
⚫Indexed Address

62. •Figure illustrates two ways of using the index mode.
In Figure (a), the index register R1 contains the
address of memory location and the value X defines
an offset (displacement) from this address to the
location where the operand is found.
• Figure(b), Here the constant X corresponds to a
memory address and the contents of the index
register define the offset of the operand.
•in either case, the effective address is the sum of two
values; one is given explicitly in the instruction and
the other is stored in a register.

63. Indexing and Arrays…
⚫Several variations:
➢X( Ri ) ; EA = [ Ri ] + X (Index)
EA is the sum of two values; one is given explicitly in the
instruction, and the other is stored in a register.
➢( Ri, Rj ) ; EA = [ Ri ] + [ Rj ] (Base with Index)
a A second register (base register) may be used to contain the
offset X. EA is the sum of the contents of registers Ri and Rj.
➢ X( Ri, Rj ) ; EA = X + [ Ri ] + [ Rj ] (Base with Index and
offset). Uses two registers plus a constant denoted as
X(Ri,Rj). The EA is the sum of the constant X and the contents
of register Ri and Rj.

64. ⚫Effective address is determined by Index mode using the
program counter in place of the general-purpose register. It
can be used to address a memory location that is X bytes
away from the location presently pointed to by the program
counter.
⚫Can be used to access data operands. But, mostly used to
specify the target address in branch instructions
⚫ X( PC ) ; EA = [ PC ] + X (X is a signed number)
eg. Branch>0 LOOP
branch target location (LOOP) is computed by specifying it
as an offset from the current value of PC
⚫Branch target may be either before or after the branch
instruction, the offset is given as a singed number.
Relative Addressing (PC-Relative)

65. CMP R1, #0 ; Compare R1 with 0
BEQ 4 ; Branch 4 instructions forward if R1 == 0
ADD R1, R2 ; 1st instruction after BEQ
SUB R3, R4 ; 2nd instruction after BEQ
MUL R4, R5 ; 3rd instruction after BEQ
MOV R6, #1 ; 4th instruction (target of BEQ)
Relative Addressing (PC-Relative) EXAMPLE
•BEQ stands for Branch if Equal.
•The instruction causes the program to jump to a specific location if a
particular condition is met
•If R1 is zero, jump to 4
th
instruction. Else continue to the next
instruction

66. The effective address of the operand is the contents of a register
specified in the instruction.
⚫After accessing the operand, the contents of this register are
automatically incremented to point to the next item in a list.
( Ri )+ → EA = [ Ri ] ;
Increment Ri
❑The increment is 1 for byte-sized operands, 2 for 16-bit operands,
and 4 for 32-bit operands.
Autoincrement mode
LDR (R0)+, R1 ; Load word from the address in R0 into R1, then increment R0 by
byte size.
Example

67. •Auto-decrement mode:
The contents of a register specified in the
instruction are first automatically decremented
and are then used as the effective address of the
operand.
The Auto-increment mode is written as -(Ri)

68. Addressing Modes
⚫The different ways in which the location of an operand is specified in
an instruction are referred to as addressing modes.

69. Fundamental Concepts
•Processor fetches one instruction at a time and perform the
operation specified.
•Instructions are fetched from successive memory locations
until a branch or a jump instruction is encountered.
•Processor keeps track of the address of the memory location
containing the next instruction to be fetched using Program
Counter (PC).
•Instruction Register (IR)- Instructions fetched from memory
are kept in IR in CPU

70. Executing an Instruction
❖Fetch phase
•Fetch the contents of the memory location pointed to by
the PC. The contents of this location are loaded into the
IR.
IR ← [[PC]]
•Assuming that the memory is byte addressable,
increment the contents of the PC by 4 (fetch phase).
PC ← [PC] + 4
❖Execution phase
•Carry out the actions specified by the instruction in the IR

71. Single Bus Organization of Processor

72. Internal organization of the processor
❑The arithmetic and logic unit (ALU) and all the registers are
interconnected through a single common bus, which is internal to
the processor.
❑The data and address lines of the external memory bus are
connected to the internal processor bus via the memory data
register, MDR, and the memory address register, MAR, respectively.
❑Register MDR has two inputs and two outputs.
Data may be loaded into MDR either from the memory bus or from
the internal processor bus. The data stored in MDR may be placed
on either bus.
❑The input of MAR is connected to the internal bus, and its output is
connected to the external bus.
❑The control lines of the memory bus are connected to the
instruction decoder and control logic block. This unit is responsible
for issuing the signals that control the operation of all the units
inside the processor and for interacting with the memory bus.

73. Internal organization of the processor
•Registers R0 through R(n-1) may be provided for general-purpose use by
the programmer.
• Three registers, Y, Z, and TEMP -They are used by the processor for
temporary storage during execution of some instructions.
•The multiplexer MUX selects either the output of register Y or a constant
value 4 to be provided as input A of the ALU.
• The constant 4 is used to increment the contents of the program counter.
•ALU: Used to perform arithmetic and logical operation.
•Data Path:
❖The registers, ALU and interconnecting bus are collectively referred to as
the data path.

74. Internal organization of the processor
•Instruction can be executed by performing one or more of the
following operations in some specified sequence:
1.Transfer a word of data from one processor register to another or
to the ALU
2.Perform an arithmetic or a logic operation and store the result in a
processor register
3.Fetch the contents of a given memory location and load them into
a processor register
4.Store a word of data from a processor register into a given memory
location

75. 1. Register Transfers
❖MOVE Ri, Rj
1.Riout=1, Rjin=1

76. •The input and output gates for register Ri are
controlled by signals Ri
in and Ri
out .
•Initially Ri
in is set to1 – data available on
common bus are loaded into Ri.
•Ri
out is set to1 – the contents of register are
placed on the bus.
•Ri
out is set to 0 – the bus can be used for
transferring data from other registers .

77. Data transfer between two registers:
EX: Transfer the contents of R1 to R4.
Enable output of register R1 by setting R1out=1. This
places the contents of R1 on the processor bus.
Enable input of register R4 by setting R4in=1. This loads
the data from the processor bus into register R4.
❖MOVE R1, R4
R1out=1, R4in=1.

78. 2. Performing an Arithmetic or Logic Operation
•The ALU is a combinational circuit that has no internal
storage.
•ALU gets the two operands from MUX and bus. The result
is temporarily stored in register Z.
•What is the sequence of operations to add the contents of
register R1 to those of R2 and store the result in R3?
•Add R1,R2,R3

79. Step 1: Output of the register R1 and input of the register Y
are enabled, causing the contents of R1 to be transferred
to Y.
Step 2: The multiplexer’s select signal is set to select Y
causing the multiplexer to gate the contents of register Y
to input A of the ALU.
Step 3: The contents of Z are transferred to the destination
register R3.
Add R1, R2, R3
1.R1out, Yin
2.R2out, Select Y, Add, Zin
3.Zout, R3in,End

80. Arithmetic Operation
❖Add R1, R2, R3
1.R1out, Yin
2.R2out, SelectY, Add, Zin
3.Zout, R3in

81. 3.Fetching a Word from Memory
•The response time of each memory access varies (cache
miss, memory-mapped I/O,…).
•To accommodate this, the processor waits until it
receives an indication that the requested operation has
been completed (Memory-Function-Completed, MFC).
•Move (R1), R2
➢MAR ← [R1]
➢Start a Read operation on the memory bus
➢Wait for the MFC response from the memory
➢Load MDR from the memory bus
➢R2 ← [MDR]

82. Fetching a Word from Memory
•Address into MAR; issue Read operation; data into MDR.
Connection and control signals for register MDR.

83. TimingFi gure 7.5.Ti m i ng of a m em ory Read operati on.
1 2
Clock
Address
MR
Data
MFC
Read
MDR
i nE
MDR
out
Step 3
MAR
in
Assume MAR is always
available on the address
lines of the memory bus.
⚫Move (R1), R2
1.R1out, MARin, Read
2.MDRinE, WMFC
3.MDRout, R2in

84. 4. Storing a word in memory
•Address is loaded into MAR
•Data to be written loaded into MDR.
•Write command is issued.
•Example:
•Move R2, (R1)
R1
out,MAR
in
R2
out,MDR
in,Write
MDR
outE, WMFC, End

85. Execution of a Complete Instruction
•Add (R3), R1
•Fetch the instruction
•Fetch the first operand (the contents of the
memory location pointed to by R3)
•Perform the addition
•Load the result into R1

86. Execution of a Complete Instruction
•Instruction execution proceeds as follows.
• step 1, the instruction fetch operation is
initiated by loading the contents of the PC
into the MAR and sending a Read request
to the memory.
• The Select signal is set to Select4, which
causes the multiplexer MUX to select the
constant 4. This value is added to the
operand at input B, which is the contents
of the PC, and the result is stored in
register Z.
• step 2,The updated value is moved from
register Z back into the PC, while waiting
for the memory to respond.
• step 3, the word fetched from the
memory is loaded into the IR.

88. Execution of a Complete Instruction
•Steps 4 The contents of register R3 are
transferred to the MAR and a memory
read operation is initiated.
•Step 5Then the contents of Rl are
transferred to register Y to prepare for
the addition operation.
•step 6 The contents of MDR are gated
to the bus, and thus also to the B input
of the ALU, and register Y is selected as
the second input to the ALU by
choosing Select Y. The sum is stored in
register Z,
• step 7 Z is transferred to Rl & End
signal causes a new instruction fetch
cycle to begin by returning to step 1

89. •Steps 1 through 3 constitute the instruction
fetch phase, which is same for all instructions.
•The instruction decoding circuit interprets the
contents of the IR at the beginning of step4.
This enables the control circuitry to activate
the control signals for steps 4 through 7,
which constitutes the execution phase.

90. Execution of Branch Instructions
❖Unconditional branch
•A branch instruction replaces the contents of PC with the
branch target address, which is usually obtained by
adding an offset X given in the branch instruction.
•The offset X is usually the difference between the branch
target address and the address immediately following the
branch instruction.
•(eg:- if the branch instruction is at location 1000 and
branch target-address is 1200, then the value of X must
be 196, since the PC will be containing the address 1004
after fetching the instruction at location 1000).

91. Execution of Unconditional Branch Instructions
Control sequence for an Unconditional branch instruction.

92. ⚫The processing starts as usual, the fetch phase ends in step 3.
⚫In step 4, offset-value is extracted from IR by instruction-decoding
circuit.
⚫Since updated value of PC is already available in register Y, offset X
is gated onto the bus, and an addition operation is performed.
⚫In step 5, the result, which is the branch-address,is loaded into PC.
❖ Conditional branch
⚫In case of conditional branch, we need to check the status of the
condition-codes before loading a new value into the PC.
⚫e.g. Offset-field-of-IRout, Select Y, Add, Zin, If N=0 then END.
⚫If N=0, processor returns to step 1 immediately after step 4.
⚫If N=1, step 5 is performed to load a new value into PC.
Execution of Branch Instructions

93. Execution of Conditional Branch Instructions
Control sequence for an Conditional branch instruction.

94. Exercise
•What is the control
sequence for
execution of the
instruction
Add R1, R2
including the
instruction fetch
phase? (Assume
single bus
architecture)lines
Data
Address
lines
bus
Memory
Carry -in
ALU
PC
MAR
MDR
Y
Z
Add
XOR
Sub
bus
IR
TEMP
R0
control
ALU
lines
Control signals
Rn1-( )
Instruction
decoder and
Internal processor
control logic
A B
Fi gure 7.1. Si ngl e-bus organi zati on of the datapath i nsi de a processor.
MUXSelect
Constant 4

95. Multiple-Bus Organization

96. • A three-bus structure used to connect the registers and the ALU of a processor.
• All general-purpose registers are combined into a single block called the register
file.
• The register file have three ports.
• There are two outputs, allowing the contents of two different registers to be
accessed simultaneously and have their contents placed on buses A and B.
• The third port allows the data on bus C to be loaded into a third register during
the same clock cycle.
• Buses A and and B are used to transfer the source operands to the A and B
inputs of the ALU, where an arithmetic or logic operation may be performed.
• The result is transferred to the destination over bus C.
•If needed, the ALU may simply pass one of its two input operands unmodified to
bus C.
• We will call the ALU control signals for such an operation R=A or R=B.
•The three-bus arrangement obviates the need for registers Y and Z .
• A second feature is the introduction of the Incremental unit, which is used to
increment the PC by 4.
•Using the incrementer eliminates the need to add the constant value 4 to the PC
using the main ALU.
•The source for the constant 4 at the ALU input multiplexer can be used to
increment other address such as loadmultiple & storemultiple
Multiple-Bus Organization

97. Multiple-Bus Organization
•Add R4, R5, R6
StepAction
1 PC
out
,R=B,MAR
in
,Read,IncPC
2 WMFC
3 MDR
outB
,R=B,IR
in
4 R4outA,R5outB,SelectA,Add,R6in,End
Figure 7.9. Control sequence for the instruction. Add R4,R5,R6,
for the three-bus organization in Figure 7.8.

98. •Step 1:The contents of PC are passed
through the ALU using R=B control signal & loaded into MAR
to start a memory read operation
At the same time PC is incremented by 4
•Step 2:The processor waits for MFC
•Step 3: Loads the data ,received into MDR ,then transfers
them to IR.
•Step 4: The execution phase of the instruction requires only
one control step to complete.